NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

• US 20130056816A1
• Filed: 03/15/2012
• Published: 03/07/2013
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Hiroyasu, Iwase, Masao
• Granted Patent: US 8,786,003 B2
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 27/0738 in combination with resistors only
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a substrate;

a memory unit provided on the substrate; and

a non-memory unit provided on the substrate to be juxtaposed with the memory unit in a plane parallel to a major surface of the substrate,

the memory unit including;

a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis;

a first semiconductor layer opposing side surfaces of the plurality of first electrode films;

a first memory film provided between the first semiconductor layer and the plurality of first electrode films; and

a first conductive film provided on the first stacked body apart from the first stacked body,

the non-memory unit including a resistance element unit of the same layer as the first conductive film.

2. The device according to claim 1, wherein:

the first semiconductor layer pierces the stacked body along the first axis; and

the first memory film is provided along the first axis around the first semiconductor layer.

3. The device according to claim 1, wherein the first conductive film is a selection gate electrode configured to control a conduction of the first semiconductor layer.

4. The device according to claim 1, wherein:

the first conductive film and the resistance element unit include polycrystalline silicon; and

an impurity concentration of the resistance element unit is lower than an impurity concentration of the first conductive film.

5. The device according to claim 1, wherein:

the first conductive film includes a silicide; and

an amount of the silicide contained in the resistance element unit is lower than an amount of the silicide contained in the first conductive film, or the resistance element unit does not include the silicide.

6. The device according to claim 1, wherein the non-memory unit includes a contact electrode provided on the resistance element unit to conduct to the resistance element unit.

7. The device according to claim 1, wherein the first memory film includes a stacked film, the stacked film including a first insulating layer including an oxide, a second insulating layer including a nitride, and a third insulating layer including an oxide stacked in this order from the first electrode films toward the first semiconductor layer.

8. The device according to claim 1, wherein the memory unit includes a plurality of the first semiconductor layers.

9. The device according to claim 1, wherein the memory unit further includes:

a second stacked body adjacent to the first stacked body in a second axis perpendicular to the first axis, the second stacked body including a plurality of second electrode films stacked in the first axis and a second inter-electrode insulating film provided between two of the second electrode films mutually adjacent along the first axis;

a second conductive film provided on the second stacked body apart from the second stacked body;

a second semiconductor layer piercing the second stacked body along the first axis;

a second memory film provided between the second semiconductor layer and the plurality of second electrode films; and

a semiconductor connection portion connecting one end of the first semiconductor layer to one end of the second semiconductor layer.

10. The device according to claim 1, wherein a thickness of the first conductive film along the first axis is equal to a thickness of the resistance element unit along the first axis.

11. The device according to claim 1, wherein the memory unit further includes an interconnect connection unit juxtaposed with the memory unit in a plane parallel to the major surface.

12. The device according to claim 1, wherein:

the memory unit includes an interconnect connection unit; and

the interconnect connection unit includes draw-out interconnects formed by extending the plurality of first electrode films in a second axis orthogonal to the first axis.

13. The device according to claim 12, wherein lengths of the draw-out interconnects along the second axis differ along the first axis between layers of the draw-out interconnects.

14. A method for manufacturing a nonvolatile semiconductor memory device, the device including a substrate, a memory unit provided on a major surface of the substrate, and a non-memory unit juxtaposed with the memory unit in a plane parallel to the major surface, the memory unit including a first stacked body, a first semiconductor layer, a first memory film, and a first conductive film, the first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis, the first semiconductor layer being provided to oppose side surfaces of the plurality of first electrode films, the first memory film being provided between the first semiconductor layer and the plurality of first electrode films, the first conductive film being provided on the first stacked body apart from the first stacked body, the non-memory unit including a resistance element unit of the same layer as the first conductive film, the method comprising:

forming a conductive film stacked body on the major surface, the conductive film stacked body including a plurality of conductive material films stacked along the first axis and an inter-layer insulating film provided between two of the conductive material films mutually adjacent along the first axis;

exposing side surfaces of the plurality of conductive material films in a first region of the conductive film stacked body used to form the memory unit;

forming the first semiconductor layer in the first region to oppose the side surfaces of the plurality of conductive material films and forming the first memory film in the first region to be provided between the first semiconductor layer and the side surfaces; and

forming the resistance element unit in a second region of the conductive film stacked body used to form the non-memory unit in a portion of the conductive material film of the uppermost layer of the plurality of conductive material films.

15. The method according to claim 14, wherein the forming of the resistance element unit includes forming the conductive material film of the uppermost layer of the plurality of conductive material films of the first region to be a selection gate electrode configured to control a conduction of the first semiconductor layer.

16. The method according to claim 14, wherein:

polycrystalline silicon is used as the conductive material film; and

the forming of the resistance element unit includes causing an impurity concentration of a portion of the conductive material film included in the second region to be lower than an impurity concentration of a portion of the conductive material films included in the first region.

17. The method according to claim 14, wherein the forming of the first memory film includes forming a silicide in a portion of the conductive material films included in the first region.