Multi-Fin Device and Method of Making Same

• US 20130056826A1
• Filed: 09/01/2011
• Published: 03/07/2013
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chi-Wen, Wang, Chao-Hsiung
• Granted Patent: US 9,287,385 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Claims

1. A device comprising:

a substrate;

a plurality of fins formed on the substrate;

source and drain regions formed in the respective fins;

a dielectric layer formed on the substrate, the dielectric layer having a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin; and

a continuous gate structure overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin.

2. The device of claim 1 wherein the device is a finFET device.

3. The device of claim 1 comprising:

a first fin having a first sidewall covered by the dielectric layer and a second sidewall that extends above the dielectric layer;

a second fin having both a first and second sidewall that extends above the dielectric layer; and

wherein the gate structure conformally overlies the second sidewall of the first fin and the first and second sidewalls of the second fin.

4. The device of claim 1 wherein each fin of the plurality of fins has a top surface having a thickness t and at least one sidewall having a height h above the dielectric layer, wherein a channel is formed in the plurality of fins, the channel having a channel width defined by sum of the thicknesses t and the sum of the heights h.

5. The device of claim 1 wherein at least one fin of the plurality of fins has two sidewalls extending above the dielectric layer.

6. The device of claim 1 includes three or more fins.

7. The device of claim 1 wherein the first thickness of the dielectric layer is equivalent to a height above the substrate of the fin.

8. The device of claim 1 wherein the plurality of fins selected from the group consisting essentially of an epitaxial material, the substrate material, and combinations thereof.

9. The device of claim 1 wherein each fin of the plurality of fins a sidewall, a portion of the sidewall being substantially orthogonal to a major surface of the substrate, and a lower portion of the sidewall being non-orthogonal to the major surface of the substrate.

10. A transistor comprising:

a first semiconductor fin in a dielectric layer, the first semiconductor fin having a first sidewall extending a first distance above the dielectric layer, a top surface, and a second sidewall extending a second distance over the dielectric layer;

a second semiconductor fin in the dielectric layer, the second fin having a first sidewall extending the first distance above the dielectric layer, a top surface, and a second sidewall extending the first distance above the dielectric layer;

a gate structure overlying the first and second semiconductor fins, wherein the gate structure contacts the first semiconductor fin on the top surface and at least one sidewall and contacts the second semiconductor fin on the top surface and at least one sidewall;

a source region distributed in the first and second semiconductor fins; and

a drain region distributed in the first and second semiconductor fins.

11. The transistor of claim 10 further comprising a third semiconductor fin in the dielectric layer, the third semiconductor fin having a first sidewall extending the first distance above the dielectric layer, a top surface, and a second sidewall extending the first distance above the dielectric layer.

12. The transistor of claim 10 wherein the second distance is equal to zero.

13. The transistor of claim 10 wherein the gate structure includes a gate dielectric and a gate electrode.

14. The transistor of claim 10 wherein the transistor includes a channel region in the first and second fins and wherein the channel region has a channel width that is equal to the sum of the two top surface thicknesses and the sum of the distances by which the first and second sidewalls of the first semiconductor fin extend above the dielectric layer and the sum of the distances by which the first and second sidewalls of the second semiconductor fin extend above the dielectric layer.

15. A method of forming a transistor comprising:

forming a plurality of fins on a substrate;

forming source and drain regions in the plurality of fins;

forming a dielectric layer between the fins;

adjusting a thickness of the dielectric layer between at least two of the plurality of fins; and

forming a continuous gate structure on the fins and dielectric layer.

16. The method of claim 15 wherein the step of forming a plurality of fins on a substrate comprises a process selected from the group consisting essentially of etching fins into a substrate and epitaxially growing fins on a substrate, and combinations thereof.

17. The method of claim 15 wherein the step of adjusting a thickness of the dielectric layer includes:

covering a portion of the dielectric layer; and

etching back a not covered portion of the dielectric layer.

18. The method of claim 17 further including:

uncovering the covered portion of the dielectric layer.

19. The method of claim 18 further including:

etching back the uncovered portion of the dielectric layer; and

further etching back the not covered portion of the dielectric layer.

20. The method of claim 15 wherein forming source and drain regions includes implanting dopants into the respective fins.