SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE

• US 20130056837A1
• Filed: 09/24/2011
• Published: 03/07/2013
• Est. Priority Date: 09/02/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Jin-Aun, Chang, Maxi, Lo, Shih-Hao, Yeh, Chih-Yang, Kao, Jung-Hui, Tu, Yuan-Tien, Lin, Huan-Just, Peng, Chih-Tang, Jeng, Pei-Ren, Young, Bao-Ru, Chuang, Hak-Lay, Yang, Jen-Sheng, Lin, Ta-Wei, Lin, Hui-Wen
• Granted Patent: US 8,822,283 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.

Claims

1. A method of making an integrated circuit, the method comprising:

providing a semiconductor substrate;

forming a gate dielectric over the substrate;

forming a metal gate structure over the semiconductor substrate and the gate dielectric;

forming a thin dielectric film on the metal gate structure, the thin dielectric film comprising oxynitride combined with metal from the metal gate;

providing an interlayer dielectric (ILD) on either side of the metal gate structure.

2. The method of claim 1, wherein the gate dielectric is a high-k dielectric.

3. The method of claim 1 wherein the metal gate structure includes a plurality of metal layers including copper and titanium.

4. The method of claim 3 wherein the thin dielectric film combines with the copper to form copper oxynitride and with the titanium to form titanium oxynitride.

5. The method of claim 1 wherein forming the thin dielectric film includes using an oxygen plasma.

6. The method of claim 5 wherein forming the thin dielectric film further includes using an ammonia plasma.

7. The method of claim 5 wherein forming the thin dielectric film further includes using a nitrogen plasma.

8. The method of claim 1 wherein the thin dielectric layer has a thickness less than about 10 nm.

9. An integrated circuit, comprising:

a semiconductor substrate;

a gate dielectric over the substrate;

a metal gate structure over the semiconductor substrate and the gate dielectric;

a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate;

an interlayer dielectric (ILD) on either side of the metal gate structure.

10. The integrated circuit of claim 9, wherein the gate dielectric is a high-k dielectric.

11. The integrated circuit of claim 9, wherein the dielectric film has a thickness less than about 10 nm.

12. The integrated circuit of claim 9, wherein the metal includes copper and the dielectric film includes copper oxynitride.

13. The integrated circuit of claim 9, wherein the metal includes at least two from the group consisting of copper, titanium, tantalum, and aluminum.

14. The integrated circuit of claim 13, wherein the dielectric film includes at least two from the group consisting of copper oxynitride, titanium oxynitride, tantalum oxynitride, aluminum oxynitride, and titanium aluminum oxynitride.

15. A method for making an integrated circuit, comprising:

providing a substrate with a high-k dielectric;

providing a polysilicon gate structure over the high-k dielectric;

forming a hardmask on a top surface of the polysilicon gate structure and sidewall structures on side surfaces of the polysilicon gate structure;

after forming the hardmask, performing a doping process on the substrate adjacent to the polysilicon gate structure;

after the doping processes, removing the hard mask and the polysilicon gate structure, but keeping at least a portion of the sidewall structures, to form a trench;

filling the trench with at least one metal material to form a metal gate;

forming a thin dielectric layer on and self aligned with a top surface of the metal gate, the thin dielectric layer including the metal material.

16. The method of claim 15, wherein the metal includes copper and the dielectric film includes copper oxynitride.

17. The method of claim 15, wherein the metal includes at least two from the group consisting of copper, titanium, tantalum, and aluminum.

18. The method of claim 17, wherein the dielectric film includes at least two from the group consisting of copper oxynitride, titanium oxynitride, tantalum oxynitride, aluminum oxynitride, and titanium aluminum oxynitride.

19. The method of claim 15, wherein the dielectric film has a thickness less than about 10 nm.

20. The method of claim 15 wherein forming the thin dielectric film includes using an oxygen plasma and a nitrogen-containing plasma.