MEMORY SYSTEM

• US 20130058145A1
• Filed: 09/05/2012
• Published: 03/07/2013
• Est. Priority Date: 09/06/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: YU, Hak-soo, KANG, Uk-song, PARK, Chul-woo, HWANG, Hong-Sun, CHOI, Joo-sun
• Granted Patent: US 8,934,311 B2
• Time in Patent Office: Days
• US Class Current: 365/49.17
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/783 with refresh of replacement cells, e.g. in DRAMs

Abstract

A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

Claims

1. A semiconductor device comprising:

a first memory region including a plurality of memory cells;

a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and

a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit,

wherein the first memory region and the second memory region include different types of memory cells.

2. The semiconductor device of claim 1, further comprising a third memory region configured to store the WBA of the first memory region in a non-volatile manner.

3. The semiconductor device of claim 1, wherein the plurality of memory cells of the first memory region include dynamic random access memory (DRAM) cells.

4. The semiconductor device of claim 3, wherein the weak bit corresponds to a memory cell from among the DRAM cells which has a weak refresh characteristic, a weak cell write characteristic, or a weak data retention characteristic.

23. The semiconductor device of claim 1, wherein the second memory region comprises:

a WBA table SRAM configured to store the WBA;

a data SRAM configured to store data intended to be stored in the WBA; and

a switch configured to switch the first memory region or the data SRAM, and

wherein the WBA table SRAM and the data SRAM are configured to communicate via an off-chip interface.

24. The semiconductor device of claim 23, wherein the second memory region further comprises:

a sideband control unit that is connected to the WBA table SRAM and is configured to deliver a sideband control data packet indicating matching of the WBA to the switch via sideband buses (SBB).

25. The semiconductor device of claim 24, wherein the sideband control unit is configured to deliver the sideband control data packet by using preamble and postamble signals.

5-22. -22. (canceled)

26-34. -34. (canceled)

35. A memory module comprising:

a module board;

at least one memory chip mounted on the module board and including a plurality of memory cells; and

a memory buffer chip mounted on the module board and configured to control operations of the at least one memory chip;

wherein the memory buffer chip includes

a test unit configured to detect a weak bit from among the plurality of memory cells;

a first memory region configured to store a weak bit address (WBA) of the at least one memory chip, and data intended to be stored in the weak bit; and

a second memory region configured to store the WBA of the at least one memory chip in a non-volatile manner, and

wherein the at least one memory chip, and the first memory region in the memory buffer chip include different types of memory cells.

36. The memory module of claim 35, wherein the test unit is configured to screen the WBA of the at least one memory chip and then, store the WBA and corresponding data in an error log register.

40. The memory module of claim 35, wherein the first memory region is configured to repair the weak bit of the at least one memory chip by a bit unit, a chip unit, a chip group unit, or a rank unit, according to data replacement granularity (DRG).

41. The memory module of claim 40, wherein the first memory region is configured to select a bit to be repaired, by using a switch control bit (SCB) that is allocated to data input/output signals (DQs) of the at least one memory chip.

42. The memory module of claim 41, wherein the first memory region is configured to select the bit to be repaired by using the DRG and the SCB, by directly mapping the bit to be repaired to the DQs.

44. The memory module of claim 35, wherein the first memory region is configured to store the WBA, and includes a content-addressable memory (CAM) configured to perform an address matching operation with respect to a request address.

45. The memory module of claim 44, wherein the address matching operation includes generating a first comparison result based on the request address and a row address of the WBA, and then, generating a second comparison result based on the request address and a column address of the WBA.

37-39. -39. (canceled)

43. (canceled)

46-69. -69. (canceled)

70. A semiconductor device comprising:

a first memory region including a plurality of RAM memory cells;

a test unit configured to detect a bit address of a weak cell from among the plurality of memory cells; and

a second memory region including a plurality of RAM cells configured to store the detected address as a weak bit address (WBA), and configured to store data addressed to be stored at the detected address.

71. The semiconductor device of claim 70, wherein the first memory region and the second memory region include different types of RAM memory cells.

72. The semiconductor device of claim 70, further comprising a third memory region that stores the WBA of the first memory region in a non-volatile manner.

73. The semiconductor device of claim 70, wherein the first memory region includes dynamic random access memory (DRAM) cells.

74. The semiconductor device of claim 73, wherein the weak cell is a cell, from among the DRAM cells, having at least one of a refresh characteristic, a write characteristic, and a data retention characteristic that is outside a reference range.

75. The semiconductor device of claim 70, wherein the second memory region includes static random access memory (SRAM) cells.