System and Method to Correlate Errors to a Specific Downstream Device in a PCIe Switching Network

• US 20130060987A1
• Filed: 09/01/2011
• Published: 03/07/2013
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Bolen, Austin, Brahmaroutu, Surender V.
• Granted Patent: US 9,086,945 B2
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A Peripheral Component Interconnect-Express (PCIe) port includes a PCIe link, a pending transaction counter, and an error status register. The PCIe port operates to issue a transaction on the PCIe link, determine that an endpoint device has become uncoupled from the PCIe link after issuing the first transaction, determine that a value stored in the pending transaction counter is not equal to zero in response to determining that the endpoint device has become uncoupled, and set an error bit in the error status register in response to determining that the first value is not equal to zero.

Claims

1. A Peripheral Component Interconnect-Express (PCIe) port comprising:

a PCIe link;

a pending transaction counter; and

an error status register;

the PCIe port being operable to;

issue a first transaction on the PCIe link;

determine that an endpoint device has become uncoupled from the PCIe link after issuing the first transaction;

determine that a first value stored in the pending transaction counter is not equal to zero in response to determining that the endpoint device has become uncoupled; and

set a first error bit in the error status register in response to determining that the first value is not equal to zero.

2. The PCIe port of claim 1, wherein the PCIe port is further operable to increment the pending transaction counter in response to issuing the first transaction.

3. The PCIe port of claim 1, wherein the PCIe port is further operable to:

issue a second transaction on the PCIe link; and

decrement the pending transaction counter in response to receiving an acknowledgement from the endpoint device indicating that the endpoint device received the second transaction.

4. The PCIe port of claim 1, further comprising:

an error mask register including a mask bit that is associated with the first error bit.

5. The PCIe port of claim 4, wherein the PCIe port is further operable to:

determine a second value stored in the mask bit.

6. The PCIe port of claim 5, wherein the PCIe port is further operable to:

send an advanced error reporting packet to a PCIe root port in response to setting the first error bit and in further response to determining that the second value is a one.

7. The PCIe port of claim 4, further comprising:

an error severity register including a severity bit that is associated with the first error bit.

8. The PCIe port of claim 1, wherein the PCIe port is further operable to:

determine that the first value is equal to zero in response to determining that the endpoint device has become uncoupled; and

set a second error bit in the error status register in response to determining that the first value is equal to zero.

9. The PCIe port of claim 8, wherein the PCIe port is further operable to:

receive a second transaction;

determine that the endpoint device has become uncoupled from the PCIe link before receiving the second transaction; and

set a third error bit in the error status register in response to determining that the endpoint device was uncoupled before receiving the second transaction.

10. A method comprising:

receiving a first transaction at a Peripheral Component Interconnect-Express (PCIe) port;

issuing the first transaction on a PCIe link of the PCIe port;

determining that an endpoint device has become uncoupled from the PCIe link after issuing the first transaction;

determining that a first value stored in a pending transaction counter is not equal to zero in response to determining that the endpoint device has become uncoupled; and

setting a first error bit in an error status register in response to determining that the first value is not equal to zero.

11. The method of claim 10, further comprising:

incrementing the pending transaction counter in response to issuing the first transaction.

12. The method of claim 10, further comprising:

issuing a second transaction on the PCIe link; and

decrementing the pending transaction counter in response to receiving an acknowledgement from the endpoint device indicating that the endpoint device received the second transaction.

13. The method of claim 10, further comprising:

determining a second value stored in a mask bit associated with the first error bit.

14. The method of claim 13, further comprising:

sending an advanced error reporting packet to a PCIe root port in response to setting the first error bit and in further response to determining that the second value is a one.

15. The method of claim 10, further comprising:

determining that the first value is equal to zero in response to determining that the endpoint device has become uncoupled; and

setting a second error bit in the error status register in response to determining that the first value is equal to zero.

16. The method of claim 15, further comprising:

receiving a second transaction;

determining that the endpoint device has become uncoupled from the PCIe link before receiving the second transaction; and

setting a third error bit in the error status register in response to determining that the endpoint device was uncoupled before receiving the second transaction.

17. Machine-executable code for an information handling system, wherein the machine-executable code is embedded in a non-transitory storage medium and includes instructions for carrying out a method, the method comprising:

receiving a first transaction at a Peripheral Component Interconnect-Express (PCIe) port;

issuing the first transaction on a PCIe link of the PCIe port;

incrementing the pending transaction counter in response to issuing the first transaction;

determining that an endpoint device has become uncoupled from the PCIe link after issuing the first transaction;

determining that a first value stored in a pending transaction counter is not equal to zero in response to determining that the endpoint device has become uncoupled; and

setting a first error bit in an error status register in response to determining that the first value is not equal to zero.

18. The machine executable code of claim 17, the method further comprising:

issuing a second transaction on the PCIe link; and

decrementing the pending transaction counter in response to receiving an acknowledgement from the endpoint device indicating that the endpoint device received the second transaction.

19. The machine executable code of claim 17, the method further comprising:

determining a second value stored in a mask bit associated with the first error bit; and

sending an advanced error reporting packet to a PCIe root port in response to setting the first error bit and in further response to determining that the second value is a one.

20. The machine executable code of claim 17, the method further comprising:

determining that the first value is equal to zero in response to determining that the endpoint device has become uncoupled;

setting a second error bit in the error status register in response to determining that the first value is equal to zero;

receiving a second transaction;

determining that the endpoint device has become uncoupled from the PCIe link before receiving the second transaction; and

setting a third error bit in the error status register in response to determining that the endpoint device was uncoupled before receiving the second transaction.