DATA MASK ENCODING IN DATA BIT INVERSION SCHEME

• US 20130061006A1
• Filed: 09/01/2011
• Published: 03/07/2013
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Hein, Thomas
• Granted Patent: US 8,706,958 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/1009 Data masking during input/output
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.

Claims

1. A system comprising:

a controller comprising an encoder,

a memory comprising a decoder,

the encoder configured to receive multiple data bits and a data mask bit and output to the memory encoded data bits and an additional bit,

the decoder configured to receive the encoded data bits and the additional bit and determine whether to invert the encoded data bits and whether to mask the encoded data bits.

2. The system of claim 1, wherein the encoder is configured to encode into the encoded data bits and the additional bit inversion information instructing to invert the encoded data bits and mask information instructing to mask the encoded data bits.

3. The system of claim 1, wherein the decoder is configured to determine whether to invert the encoded data bits and whether to mask the encoded data bits based only on the encoded data bits and the additional bit.

4. The system of claim 3, wherein the decoder is configured to determine whether to mask the encoded data bits based on whether the encoded data bits and the additional bit comply with a DBI-DC scheme.

5. The system of claim 3, wherein the decoder is configured to determine whether to mask the encoded data bits based on whether the encoded data bits and the additional bit comply with a DBI-AC scheme.

6. The system of claim 1, wherein the decoder is configured to determine whether to mask the encoded data bits based only on the encoded data bits.

7. The system of claim 6, wherein the decoder is configured to determine whether to mask the encoded data bits based on whether the encoded data bits comply with a DBI-DC scheme.

8. The system of claim 6, wherein the decoder is configured to determine whether to mask the encoded data bits based on whether the encoded data bits comply with a DBI-AC scheme.

9. The system of claim 1, wherein the decoder is configured to determine whether to mask the encoded data bits based on whether the encoded data bits match a predetermined pattern signifying a data mask instruction.

10. The system of claim 1, wherein the encoder is configured to encode the multiple data bits into encoded data bits signifying a data mask instruction such that the encoded data bits are noncompliant with a DBI-DC or DBI-AC scheme by more than one bit.

11. A method comprising:

receiving multiple data bits and a data mask instruction,

when the data mask instruction indicates to mask the multiple data bits, outputting encoded data bits and an additional bit which together instruct to mask the encoded data bits,

when the data mask instruction indicates not to mask the multiple data bits, determining whether to invert the multiple data bits and outputting the multiple data bits in inverted or non-inverted form and the additional bit, wherein the additional bit indicates whether the outputted multiple data bits have been inverted.

12. The method of claim 11, comprising:

receiving the encoded data bits and the additional bit,

determining whether the encoded data bits and additional bit comply with a DBI-DC scheme,

masking the encoded data bits when determined that the encoded data bits and additional bit do not comply with the DBI-DC scheme.

13. The method of claim 11, comprising:

receiving the encoded data bits and the additional bit,

determining whether the encoded data bits and additional bit comply with a DBI-AC scheme,

masking the encoded data bits when determined that the encoded data bits and additional bit do not comply with the DBI-AC scheme.

14. The method of claim 11, comprising:

receiving the encoded data bits and the additional bit,

determining whether the encoded data bits comply with a DBI-DC scheme,

masking the encoded data bits when determined that the encoded data bits do not comply with the DBI-DC scheme.

15. The method of claim 11, comprising:

receiving the encoded data bits and the additional bit,

determining whether the encoded data bits comply with a DBI-AC scheme,

masking the encoded data bits when determined that the encoded data bits do not comply with the DBI-AC scheme.

16. The method of claim 11, comprising:

receiving the multiple data bits in inverted or non-inverted form and the additional bit,

determining whether to invert the multiple data bits based on the additional bit,

inverting the multiple data bits if determined to invert the multiple data bits,

writing the multiple data bits to memory.

17. The method of claim 11, comprising determining whether to mask the encoded data bits based on whether the encoded data bits match a predetermined pattern signifying a data mask instruction.

18. The method of claim 11, wherein the step of outputting encoded data bits comprises encoding the multiple data bits into encoded data bits signifying a data mask instruction such that the encoded data bits are noncompliant with a DBI-DC or DBI-AC scheme by more than one bit.