SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20130062683A1
• Filed: 03/23/2012
• Published: 03/14/2013
• Est. Priority Date: 09/09/2011
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Yoshiaki Fukuzumi
• Inventors: FUKUZUMI, Yoshiaki, Kito, Masaru, Imamura, Takeshi
• Granted Patent: US 8,692,312 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.

Claims

1. A method of manufacturing a semiconductor memory device comprising:

forming, on a substrate, a laminated body in which a first silicon layer having an impurity concentration of a first concentration, a first sacrificial layer having an impurity concentration of a second concentration lower than the first concentration, a second silicon layer having an impurity concentration of the first concentration, and a second sacrificial layer having an impurity concentration of the second concentration are laminated in turn;

forming a first insulating film on the laminated body;

forming a trench in the laminated body, and the first insulating film;

filling a third sacrificial layer having an impurity concentration of a third concentration lower than the first concentration, and higher than the second concentration into the trench;

etching the third sacrificial layer in the trench by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer which are exposed to the inside of the trench;

etching end faces of the first silicon layer and the second silicon layer which are exposed to the inside of the trench along the end faces of the first sacrificial layer and the second sacrificial layer;

removing, after the etching of the first silicon layer and the second silicon layer, the first insulating film;

filling, after the removal of the first insulating film, a second insulating film into the trench to cover an whole surface of the first sacrificial layer, the second sacrificial layer, the first silicon layer, and the second silicon layer;

removing the first sacrificial layer and the second sacrificial layer to thereby form a gap between first silicon layer, the second silicon layer, and the second insulating film;

filling a third insulating film into the gap; and

forming a first contact connected to the first silicon layer and a second contact connected to the second silicon layer.

2. The method of claim 1, wherein the impurity is boron.

3. The method of claim 1, further comprising forming, before forming the second insulating film, a fourth insulating film to cover the whole surface of the first sacrificial layer, the second sacrificial layer, the first silicon layer, and the second silicon layer.

4. The method of claim 1, wherein the fourth insulating film is a silicon nitride film.

5. The method of claim 1, further comprising forming a hole penetrating the laminated body in a direction perpendicular to a surface of the substrate,

wherein the formation of the gap is carried out by removing the first sacrificial layer, and the second sacrificial layer by wet etching to be carried out through the hole.

6. The method of claim 5, further comprising:

forming a block insulating film on the inner surface of the hole, and on the inner surface of the gap;

forming a charge storage layer on the block insulating film; and

forming a tunnel insulating film on the charge storage layer,

wherein the third insulating film is the block insulating film formed on the inner surface of the gap.

7. The method of claim 6, wherein the third insulating film is a laminated film including at least a first silicon oxide film, a silicon nitride film, and a second silicon oxide film formed on the inner surface of the gap in turn.

8. The method of claim 1, wherein

forming the first contact, and the second contact comprises

forming a first contact hole reaching the first silicon layer, and a second contact hole reaching the second silicon layer in the second insulating film, and the third insulating film, and

filling a conductive material into the first contact hole, and the second contact hole, and

in the formation of the first contact hole, and the second contact hole, the third insulating film functions as an etching stopper.

9. The method of claim 1, wherein in the etching of the end faces of the first sacrificial layer and the second sacrificial layer, a difference in retreat amount between the end face of the first sacrificial layer and the end face of the second sacrificial layer is adjusted by controlling the second concentration.

10. The method of claim 1, wherein the etching of the end faces of the first sacrificial layer and the second sacrificial layer is carried out by wet etching using an alkaline solution.

11. The method of claim 1, wherein the etching of the end faces of the first silicon layer and the second silicon layer is carried out by CDE.

12. The method of claim 1, wherein the first insulating film is a boron-added silicon oxide film.

13. The method of claim 1, wherein the second concentration is 0.

14. A semiconductor memory device comprising:

a substrate;

a laminated body including a first silicon layer, a first insulating film, a second silicon layer, and a second insulating film which are laminated on the substrate in turn, and including a hole penetrating the laminated body in a direction perpendicular to a surface of the substrate;

a block insulating film formed on the inner surface of the hole;

a charge storage layer formed on the block insulating film;

a tunnel insulating film formed on the charge storage layer; and

a semiconductor layer formed on the tunnel insulating film,

wherein the first silicon layer and the second silicon layer are formed stepwise in such a manner that end faces of the first silicon layer and the second silicon layer differ from each other in position, and

an end face of the first insulating film is formed to protrude from the end face of the first silicon layer, and an end face of the second insulating film is formed to protrude from the end face of the second silicon layer.

15. The device of claim 14, wherein the end face of each of the first silicon layer, the first insulating film, the second silicon layer, and the second insulating film is formed into a sloped shape extending from the upper side toward the lower side.

16. The device of claim 15, wherein the end face of each of the first silicon layer, the first insulating film, the second silicon layer, and the second insulating film extends from the upper side toward the lower side curvilinearly and continuously.

17. The device of claim 14, wherein the first insulating film and the second insulating film are each integral with the block insulating film.

18. The device of claim 17, wherein each of the first insulating film and the second insulating film includes a laminated structure formed by laminating at least a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in turn from the outermost surface side.

19. The device of claim 14, further comprising a third insulating film covering the whole surface of the first silicon layer, the first insulating film, the second silicon layer, and the second insulating film at the end part.

20. The device of claim 14, wherein the third insulating film is a silicon nitride film.