Driver Circuitry for Displays
First Claim
1. Driver circuitry for producing gate line signals that are applied to gate lines in a display, the driver circuitry comprising:
- at least one clock path configured to carry clock signals with adjustable transition times;
a plurality of latches; and
a plurality of output circuits that receive the clock signals with adjustable transition times from the at least one clock path and that receive signals from the latches, wherein the plurality of latches and output circuits are organized in a plurality of rows and wherein the output circuit in each row supplies a received clock signal to a gate line in that row to serve as a gate line signal for that row.
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Accused Products
Abstract
An electronic device display may have an array of display pixels. Each pixel may receive display data on a data line and may have a thin-film transistor that is controlled by a gate line signal on a gate line. The transistors may be controlled to apply electric fields across liquid crystal material. A common electrode may be used to distribute common electrode signals to the display pixels. The display may have a segmented common electrode with isolated regions that serve as respective touch sensor electrodes. A display may include a display driver integrated circuit that is adjusted to produce clock signals with desired rise and fall times. Gate driver circuitry such as thin-film transistor circuitry may include pass transistors controlled by latches. The pass transistors may be used in providing the clock signals with the adjusted rise and fall times to the gate lines to serve as gate line signals.
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Citations
22 Claims
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1. Driver circuitry for producing gate line signals that are applied to gate lines in a display, the driver circuitry comprising:
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at least one clock path configured to carry clock signals with adjustable transition times; a plurality of latches; and a plurality of output circuits that receive the clock signals with adjustable transition times from the at least one clock path and that receive signals from the latches, wherein the plurality of latches and output circuits are organized in a plurality of rows and wherein the output circuit in each row supplies a received clock signal to a gate line in that row to serve as a gate line signal for that row. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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with a display driver circuit in a display, receiving settings that adjust a clock signal transition time; with the display driver circuit, providing clock signals with the adjusted clock signal transition time from the display driver circuit to gate driver circuitry; and with the gate driver circuitry, using the clock signals with the adjusted clock signal transition time to produce gate line signals for the display that have the adjusted clock signal transition time. - View Dependent Claims (16, 17)
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18. A display, comprising:
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an array of display pixels configured to receive display image data on data lines and having thin-film transistors controlled by gate line signals on gate lines; and display driver circuitry that produces clock signals with adjustable rise and fall times; and gate driver circuitry that receives the clock signals from the display driver circuitry and provides them to the gate lines to serve as the gate line signals. - View Dependent Claims (19, 20, 21, 22)
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Specification