SYSTEM AND MEMORY MODULE

• US 20130063998A1
• Filed: 09/11/2012
• Published: 03/14/2013
• Est. Priority Date: 09/13/2011
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: HARASHIMA, Shiro
• Granted Patent: US 8,773,883 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.

Claims

1. A system, comprising:

a controller;

a first memory module connected to the controller through a first data bus; and

a second memory module connected to the controller through a second data bus that is electrically disconnected from the first data bus, wherein

the first memory module comprises;

a first memory chip and a second memory chip;

a first data terminal connected to the first data bus; and

a first switch unit that switches over electrical connection of the first data terminal with either the first memory chip or the second memory chip, and

the second memory module comprises;

a third memory chip and a fourth memory chip;

a second data terminal connected to the second data bus; and

a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.

2. The system according to claim 1, wherein

the first memory module has the first memory chip on a first surface of a first module substrate and the second memory chip on a second surface of the first module substrate;

and

the second memory module has the third memory chip on a first surface of a second module substrate and the fourth memory chip on a second surface of the second module substrate.

3. The system according to claim 2, wherein

the first memory module has the first data terminal on the first surface of the first module substrate;

and

the second memory module has the second data terminal on the first surface of the second module substrate.

4. The system according to claim 3, wherein

the first memory module has the first switch unit between the first memory chip and the first data terminal, on the first surface of the first module substrate;

and

the second memory module has the second switch unit between the third memory chip and the second data terminal, on the first surface of the second module substrate.

5. The system according to claim 1, wherein

the first switch unit has a function of buffering data to be exchanged between the controller and the first memory chip or the second memory chip;

and

the second switch unit has a function of buffering data to be exchanged between the controller and the third memory chip or the fourth memory chip.

6. The system according to claim 1, wherein

the first memory chip and the third memory chip operate when a first chip select signal is active;

the second memory chip and the fourth memory chip operate when a second chip select signal is active; and

when one of the first chip select signal and the second chip select signal is active, the other is inactive.

7. The system according to claim 1, wherein

each of the first memory module and the second memory module includes a register that buffers a command/address signal.

8. The system according to claim 1, wherein

the first switch unit is a cross-bus switch that electrically connects one of the first memory chip and the second memory chip to the first data terminal and the other to a data terminal that is electrically connectable to the second data bus, and

the second switch unit is a cross-bus switch that electrically connects one of the third memory chip and the fourth memory chip to the second data terminal and the other to a data terminal that is electrically connectable to the first data bus.

9. The system according to claim 1, wherein

the first memory module comprises a plurality of the first memory chips, a plurality of the second memory chips, and a plurality of the first data terminals;

and

the first switch unit switches over electrical connection of the first data terminals with either the plurality of the first memory chips or the plurality of the second memory chips.

10. The system according to claim 1, further comprising:

a third memory module connected to the controller through the first data bus; and

a fourth memory module connected to the controller through the second data bus, wherein

the third memory module comprises;

a fifth memory chip and a sixth memory chip;

a third data terminal connected to the first data bus; and

a third switch unit that switches over electrical connection of the third data terminal with either the fifth memory chip or the sixth memory chip, and

the fourth memory module comprise;

a seventh memory chip and an eighth memory chip;

a fourth data terminal connected to the second data bus; and

a fourth switch unit that switches over electrical connection of the fourth data terminal with either the seventh memory chip or the eighth memory chip.

11. A memory module, in a system that includes a controller,

wherein said memory module is included a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus that is electrically disconnected from the first data bus, said memory module being the first memory module and comprising:

a first memory chip and a second memory chip;

a data terminal connected to the first data bus; and

a switch unit that switches over electrical connection of the data terminal with either the first memory chip or the second memory chip.

12. The memory module according to claim 11, wherein

the memory module has the first memory chip on a first surface of a module substrate and the second memory module on a second surface of the module substrate.

13. The memory module according to claim 12, wherein

the data terminal is provided on the first surface of the module substrate.

14. The memory module according to claim 13, wherein

the switch unit is provided between the first memory chip and the data terminal, on the first surface of the module substrate.

15. The memory module according to claim 11, wherein

the switch unit has a function of buffering data to be exchanged between the controller and the first memory chip or the second memory chip.

16. The memory module according to claim 11, wherein

the first memory chip operates when a first chip select signal is active;

the second memory chip operates when a second chip select signal is active; and

when one of the first chip select signal and the second chip select signal is active, the other is inactive.

17. The memory module according to claim 11, further comprising:

a register that buffers a command/address signal.

18. The memory module according to claim 11, wherein

the switch unit is a cross-bus switch that electrically connects one of the first memory chip and the second memory chip to the data terminal and the other to a data terminal that is electrically connectable to the second data bus.

19. The memory module according to claim 11, comprising:

a plurality of the first memory chips, a plurality of the second memory chips, and a plurality of the data terminals;

the switch unit switches over electrical connection of the plurality of the first data terminals with either the plurality of the first memory chips or the plurality of the second memory chips.