Adaptive Read Wordline Voltage Boosting Apparatus and Method for Multi-Port SRAM
First Claim
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1. An apparatus comprising:
- a rail having a supply voltage;
a memory cell coupled to the rail;
a voltage boost generator to generate a boosted supply voltage provided to the memory cell;
a control circuit to provide a trigger signal and a reference-latch signal in response to a clock signal, wherein the reference-latch signal is delayed relative to the trigger signal;
a delay circuit coupled to the control circuit to delay the trigger signal;
an array of memory cells having a word-line input port coupled to the delay circuit to receive the delayed trigger signal, the array of memory cells to provide a set of read bit-line signals in response to the delayed trigger signal;
a latch comprising a reference-latch input port to receive the reference-latch signal, a set of latch input ports to receive the set of read bit-line signals, and an output port to signal to the voltage boost generator when the boosted supply voltage is to be greater than the supply voltage.
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Abstract
Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.
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Citations
28 Claims
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1. An apparatus comprising:
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a rail having a supply voltage; a memory cell coupled to the rail; a voltage boost generator to generate a boosted supply voltage provided to the memory cell; a control circuit to provide a trigger signal and a reference-latch signal in response to a clock signal, wherein the reference-latch signal is delayed relative to the trigger signal; a delay circuit coupled to the control circuit to delay the trigger signal; an array of memory cells having a word-line input port coupled to the delay circuit to receive the delayed trigger signal, the array of memory cells to provide a set of read bit-line signals in response to the delayed trigger signal; a latch comprising a reference-latch input port to receive the reference-latch signal, a set of latch input ports to receive the set of read bit-line signals, and an output port to signal to the voltage boost generator when the boosted supply voltage is to be greater than the supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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asserting a trigger signal in response to a clock signal; asserting a reference-latch signal delayed relative to the trigger signal; providing the trigger signal to a critical path that simulates a read path of a memory cell; boosting a supply voltage applied to a word line of the memory cell during a read operation if an output of the critical path is a logical high when the reference latch-signal is a logical high. - View Dependent Claims (13, 14, 15, 16, 17)
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18. An apparatus comprising:
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a rail having a supply voltage; a memory cell coupled to the rail; means for boosting the supply voltage to the memory cell; means for asserting a trigger signal and a reference-latch signal in response to a clock signal, wherein the reference-latch signal is delayed relative to the trigger signal; means for delaying the trigger signal; an array of memory cells having a word-line input port coupled to the delay circuit to receive the delayed trigger signal, the array of memory cells to provide a set of read bit-line signals in response to the delayed trigger signal; means for latching comprising a reference-latch input port to receive the reference-latch signal, a set of latch input ports to receive the set of read bit-line signals, and an output port to cause the means for boosting the supply voltage to boost the supply voltage to be greater than the supply voltage. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification