Adaptive Read Wordline Voltage Boosting Apparatus and Method for Multi-Port SRAM

• US 20130064031A1
• Filed: 07/09/2012
• Published: 03/14/2013
• Est. Priority Date: 09/12/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Phan, Michael ThaiThanh, Garg, Manish, Hoff, David Paul, Nguyen, Quan
• Granted Patent: US 8,659,972 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

Claims

1. An apparatus comprising:

a rail having a supply voltage;

a memory cell coupled to the rail;

a voltage boost generator to generate a boosted supply voltage provided to the memory cell;

a control circuit to provide a trigger signal and a reference-latch signal in response to a clock signal, wherein the reference-latch signal is delayed relative to the trigger signal;

a delay circuit coupled to the control circuit to delay the trigger signal;

an array of memory cells having a word-line input port coupled to the delay circuit to receive the delayed trigger signal, the array of memory cells to provide a set of read bit-line signals in response to the delayed trigger signal;

a latch comprising a reference-latch input port to receive the reference-latch signal, a set of latch input ports to receive the set of read bit-line signals, and an output port to signal to the voltage boost generator when the boosted supply voltage is to be greater than the supply voltage.

2. The apparatus as claimed in claim 1, wherein the delay circuit is programmable.

3. The apparatus as claimed in claim 1, wherein the word-line input port is selected from the group consisting of a read word-line input port and a write word-line input port.

4. The apparatus as claimed in claim 1, the array of memory cells comprising memory cells having the same layout as the memory cell.

5. The apparatus as claimed in claim 1, the array of memory cells comprising memory cells connected in series.

6. The apparatus as claimed in claim 1, the array of memory cells comprising memory cells connected in parallel.

7. The apparatus as claimed in claim 1, the memory cell comprising a read word-line connected to the voltage boost generator to receive the boosted supply voltage.

8. The apparatus as claimed in claim 7, the array of memory cells comprising memory cells, each having the same layout as the memory cell.

9. The apparatus as claimed in claim 8, wherein the word-line input port is selected from the group consisting of a read word-line input port and a write word-line input port.

10. The apparatus as claimed in claim 9, the clock signal having a clock period, wherein the control circuit delays the reference-latch signal relative to the trigger signal by one clock period.

11. The apparatus as claimed in claim 1, the clock signal having a clock period, wherein the control circuit delays the reference-latch signal relative to the trigger signal by one clock period.

12. A method comprising:

asserting a trigger signal in response to a clock signal;

asserting a reference-latch signal delayed relative to the trigger signal;

providing the trigger signal to a critical path that simulates a read path of a memory cell;

boosting a supply voltage applied to a word line of the memory cell during a read operation if an output of the critical path is a logical high when the reference latch-signal is a logical high.

13. The method as claimed in claim 12, further comprising:

delaying the trigger signal by a delay circuit.

14. The method as claimed in claim 13, further comprising:

programming the delay circuit to delay the trigger signal.

15. The method as claimed in claim 12, wherein the critical path comprises an array of memory cells, each having the same layout as the memory cell.

16. The method as claimed in claim 15, wherein the array of memory cells comprises memory cells connected in parallel.

17. The method as claimed in claim 15, wherein the array of memory cells comprises memory cells connected in series.

18. An apparatus comprising:

a rail having a supply voltage;

a memory cell coupled to the rail;

means for boosting the supply voltage to the memory cell;

means for asserting a trigger signal and a reference-latch signal in response to a clock signal, wherein the reference-latch signal is delayed relative to the trigger signal;

means for delaying the trigger signal;

an array of memory cells having a word-line input port coupled to the delay circuit to receive the delayed trigger signal, the array of memory cells to provide a set of read bit-line signals in response to the delayed trigger signal;

means for latching comprising a reference-latch input port to receive the reference-latch signal, a set of latch input ports to receive the set of read bit-line signals, and an output port to cause the means for boosting the supply voltage to boost the supply voltage to be greater than the supply voltage.

19. The apparatus as claimed in claim 18, wherein means for delaying is programmable.

20. The apparatus as claimed in claim 18, wherein the word-line input port is selected from the group consisting of a read word-line input port and a write word-line input port.

21. The apparatus as claimed in claim 18, the array of memory cells comprising memory cells having the same layout as the memory cell.

22. The apparatus as claimed in claim 18, the array of memory cells comprising memory cells connected in series.

23. The apparatus as claimed in claim 18, the array of memory cells comprising memory cells connected in parallel.

24. The apparatus as claimed in claim 18, the memory cell comprising a read word-line connected to the means for boosting the supply voltage.

25. The apparatus as claimed in claim 24, the array of memory cells comprising memory cells, each haying the same layout as the memory cell.

26. The apparatus as claimed in claim 25, wherein the word-line input port is selected from the group consisting of a read word-line input port and a write word-line input port.

27. The apparatus as claimed in claim 26, the clock signal having a clock period, wherein the means for providing the trigger signal and the reference-latch signal, and the means for delaying, delay the reference-latch signal relative to the delayed trigger signal by one clock period.

28. The apparatus as claimed in claim 18, the clock signal having a clock period, wherein the means for providing the trigger signal and the reference-latch signal, and the means for delaying, delay the reference-latch signal relative to the delayed trigger signal by one clock period.