COMPACT, ENERGY-EFFICIENT ULTRASOUND IMAGING PROBES USING CMUT ARRAYS WITH INTEGRATED ELECTRONICS

• US 20130064043A1
• Filed: 03/05/2012
• Published: 03/14/2013
• Est. Priority Date: 03/04/2011
• Status: Active Grant

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Karaman, Mustafa, DEGERTEKIN, F. Levent, Gurun, Gokce, Hasler, Jennifer O.
• Granted Patent: US 8,891,334 B2
• Time in Patent Office: Days
• US Class Current: 367/137
• CPC Class Codes: B06B 1/0215 for generating pulses, e.g. bursts of oscillations, envelopes
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B06B 2201/20 Application to multi-element transducer
• CPC Class Codes: B06B 2201/76 Medical, dental
• CPC Class Codes: G01S 15/8925 the array being a two-dimensional transducer configuration, i.e. matrix or orthogonal linear arrays
• CPC Class Codes: G01S 15/8993 Three dimensional imaging systems
• CPC Class Codes: G01S 7/5202 for pulse systems
• CPC Class Codes: G01S 7/52025 for pulse systems G01S7/52034 takes precedence
• CPC Class Codes: G01S 7/52096 related to power management, e.g. saving power or prolonging life of electronic components details of power supplies for ultrasonic medical diagnostic imaging devices A61B8/56
• CPC Class Codes: H04R 17/00 Piezoelectric transducers; Electrostrictive transducers piezoelectric or electrostrictive elements in general H10N30/00; details of piezoelectric or electrostrictive motors, generators or positioners H10N30/00

Abstract

A CMUT on CMOS imaging chip is disclosed. The imaging chip can use direct connection, CMOS architecture to minimize both internal and external connection complexity. Intelligent power management can enable the chip to be used for various imaging applications with strict power constraints, including forward-looking intra-vascular ultrasound imaging. The chip can use digital logic to control transmit and receive events to minimize power consumption and maximize image resolution. The chip can be integrated into a probe, or catheter, and requires minimal external connections. The chip can comprise integrated temperature control to prevent overheating.

Claims

1. A CMUT on CMOS chip for imaging applications comprising:

a CMOS chip comprising;

a plurality of CMUT transmit elements and associated driving circuitry;

a plurality of CMUT receive elements and associated detection circuitry; and

a digital control unit;

wherein the digital control unit cycles the plurality of transmit elements on and off in a first sequence;

wherein the digital control unit cycles the plurality of receive elements on and off in a second sequence; and

wherein the digital control unit cycles the transmit and receive elements on and off until a predetermined number of transmit and receive elements have been cycled.

2. The CMUT on CMOS chip of claim 1, wherein the first sequence cycles through the plurality of transmit elements one at a time.

3. The CMUT on CMOS chip of claim 1, wherein the first sequence cycles through the plurality of transmit elements two or more at a time.

4. The CMUT on CMOS chip of claim 3, wherein the second sequence cycles through the plurality of receive elements four at a time.

5. The CMUT on CMOS chip of claim 1, wherein the second sequence cycles through the plurality of receive elements two or more at a time.

6. The CMUT on CMOS chip of claim 1, wherein the second sequence cycles through the plurality of receive elements two or more at a time and all the receive electronics for non-selected receiver elements are turned off.

7. The CMUT on CMOS chip of claim 1 wherein the digital control unit comprises a multi-bit counter.

8. The CMUT on CMOS chip of claim 1, wherein the predetermined number is reached when all of the transmit and receive elements have been cycled on and off.

9. The CMUT on CMOS chip of claim 1, wherein the predetermined number is reached when between approximately 10 to 80 percent of the transmit and receive elements have been cycled on an off.

10. The CMUT on CMOS chip of claim 1, further comprising 13 or fewer external connections for data input, data output, and power.

11. The CMUT on CMOS chip of claim 1, further comprising eight external connections for data input, data output, and power.

12. The CMUT on CMOS chip of claim 1, further comprising:

a temperature sensor; and

a switch;

wherein, when the temperature sensor reaches a predetermined temperature, the switch interrupts power to the CMOS chip to prevent overheating.

13. The CMUT on CMOS chip of claim 12, wherein the switch is a MOS transistor.

14. A CMUT on CMOS chip for imaging applications comprising:

a CMOS chip comprising;

a first ring comprising a plurality of CMUT transmit elements disposed proximate an outer edge of the CMOS chip;

a second ring comprising a plurality of CMUT receive elements disposed proximate the outer edge of the CMOS chip; and

a digital control unit;

wherein the digital control unit activates the CMUT transmit elements one at a time to transmit an ultrasonic signal;

wherein the digital control unit activates the CMUT receive elements in groups to receive the ultrasonic signal; and

wherein an imaging cycle is complete when a predetermined number of transmit and receive elements have been activated.

15. The CMUT on CMOS chip of claim 14, wherein the first ring is disposed outside the second ring.

16. The CMUT on CMOS chip of claim 14, wherein the second ring is disposed outside the first ring.

17. The CMUT on CMOS chip of claim 14, wherein the CMUT receive elements are activated in groups of four or more.

18. A method for providing energy-efficient ultrasound imaging comprising:

providing a CMOS chip comprising;

a first ring comprising a plurality of CMUT transmit elements disposed proximate an outer edge of the CMOS chip;

an second ring comprising a plurality of CMUT transmit/receive elements proximate the outer edge of the CMOS chip; and

cycling the plurality of transmit elements on and off in a first sequence;

cycling the plurality of receive elements on and off in a second sequence;

wherein an imaging cycle is complete when a predetermined number of transmit and receive elements have been activated.

19. The method of claim 18, wherein the first sequence cycles the transmit elements on and off one at a time.

20. The method of claim 18, wherein the second sequence cycles the receive elements on and off two or more at a time.

21. The method of claim 20, wherein the second sequence cycles the receive elements on and off four at a time.

22. The method of claim 18, wherein the predetermined number is reached when all of the transmit and receive elements have been cycled on and off.

23. The method of claim 18, wherein the predetermined number is reached when approximately 10 to 80 percent of the transmit and receive elements have been cycled on and off.

24. The method of claim 18, further comprising:

sensing the temperature of the CMOS chip with a temperature sensor; and

turning the receive elements, the transmit elements, or both, off at a predetermined temperature.

25. The method of claim 24, wherein the predetermined temperature is between 35 and 50 degrees Celsius.

26. The method of claim 25, wherein the predetermined temperature is approximately 42 degrees Celsius.