STANDBY OPERATION WITH ADDITIONAL MICRO-CONTROLLER

• US 20130067259A1
• Filed: 09/08/2011
• Published: 03/14/2013
• Est. Priority Date: 09/08/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Freiwald, Axel, Mathews, Bejoy, Wiley, Edward
• Granted Patent: US 9,021,284 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

One embodiment of the present invention relates to a low-power micro-controller unit having both a standby micro-controller optimized for low power consumption and a main micro-controller optimized for high performance. A power supply is coupled to the main micro-controller and the standby micro-controller. The power supply provides power to one or more of the low-power, standby micro-controller and the high performance, main micro-controller by separate power supply paths, depending on system needs. The separate power supply paths allow the main micro-controller and the standby micro-controller operate independent of each other. During a low-power standby operating mode, power can be disconnected to the main micro-controller, while providing power to the standby micro-controller, thereby eliminating the leakage current associated with the large number of transistors in the main micro-controller, while still retaining the computational capabilities of the standby micro-controller.

Claims

1. A micro-controller unit configured to operate in a normal operating mode and a standby operating mode, comprising:

a main micro-controller configured to process data during the normal operating mode;

a standby micro-controller configured to output a wake-up signal upon detection of a predetermined event; and

a power supply coupled to the main micro-controller and the standby micro-controller by separate power supply paths and configured to selectively provide power to the main micro-controller based upon the wake-up signal;

wherein during the standby operating mode, the main micro-controller is operated in a reduced leakage state having reduced computational capabilities and power is provided to the standby micro-controller, thereby reducing leakage currents associated with transistors in the main micro-controller, while retaining computational capabilities of the standby micro-controller.

2. The micro-controller unit of claim 1, wherein the reduced leakage state is achieved by selectively providing bias voltages to one or more wells of semiconductor devices within the main micro-controller to reduce leakage currents of the semiconductor device.

3. The micro-controller unit of claim 1, wherein the reduced leakage state is achieved by not providing power to the main micro-controller, thereby eliminating leakage currents of semiconductor devices within the main micro-controller.

4. The micro-controller unit of claim 1, wherein the reduced leakage state is achieved by reducing the voltage provided to the main micro-controller, thereby reducing leakage currents of semiconductor devices within the main micro-controller.

5. The micro-controller unit of claim 1, further comprising a communication interface configured to provide for communication between the main micro-controller and the standby micro-controller during the normal operating mode.

6. The micro-controller unit of claim 5, wherein the standby micro-controller is configured to receive commands, code, or data from the main micro-controller, via the communication interface, which controls operation of the standby micro-controller during the standby operating mode.

7. The micro-controller of claim 1, further comprising:

an integrated chip package containing the main micro-controller, the standby micro-controller, and the power supply on a single silicon substrate,

wherein the main micro-controller and the standby micro-controller share one or more input/output pins of the integrated chip package.

8. A micro-controller unit, comprising:

a main micro-controller;

a standby micro-controller;

a communication interface configured to enable communication between the main micro-controller and the standby micro-controller during a normal operating mode; and

a power supply selectively coupled to the main micro-controller and to the standby micro-controller by a power regulation apparatus;

wherein during a standby operating mode, the regulation apparatus disconnects the power supply from the main micro-controller and connects the power supply to the standby micro-controller, so that the standby controller is enabled to send a wake-up signal to the power regulation apparatus that causes the micro-controller unit to enter the normal operating mode in which the power supply is connected to the main micro-controller.

9. The micro-controller unit of claim 8, wherein the standby micro-controller is configured to receive commands or code from the main micro-controller that controls operation of the standby micro-controller during the standby operating mode.

10. The micro-controller unit of claim 9, wherein the standby micro-controller comprises:

a micro-controller configured to perform data processing; and

a memory unit coupled to the micro-controller and configured to store the code and data written by the main micro-controller.

11. The micro-controller of claim 10, wherein the main micro-controller is configured to interrupt operation of the micro-controller to communicate commands or code to the memory unit by:

sending and holding a reset signal to the micro-controller to stop operation of the standby micro-controller;

communicating commands or code to the memory unit within the standby micro-controller; and

releasing the reset signal to resume operation of the micro-controller.

12. The micro-controller unit of claim 8,

wherein the main micro-controller, the standby micro-controller, and the power supply are comprised within a single silicon substrate;

wherein the single silicon substrate is contained within a single integrated chip package, and

wherein the main micro-controller and the standby micro-controller share one or more input/output pins of the single integrated chip package.

13. The micro-controller unit of claim 8,

wherein the main micro-controller is disposed on a first silicon substrate and the standby micro-controller is disposed on a separate second silicon substrate, and

wherein the first and second silicon substrates are contained within a single integrated chip package.

14. The micro-controller unit of claim 8,

wherein the standby micro-controller further comprises a status register configured to store one or more status bits, indicative of an event causing the standby micro-controller to send the wake-up signal, which are read by the main micro-controller when the power supply is connected to the main micro-controller.

15. The micro-controller unit of claim 14,

wherein the event comprises reception of a command that cannot be sufficiently processed by the first processing speed of the standby micro-controller or reception a task that is assigned to the main micro-controller.

16. The micro-controller unit of claim 8, wherein the power supply comprises:

a first power supply configured to selectively provide power to the main micro-controller by way of a first power supply path; and

a second power supply separate from the first power supply and configured to provide power to the standby micro-controller by way of a second power supply path.

17. A method for operating a micro-controller unit, comprising:

operating a standby micro-controller in a standby operating mode in which a main micro-controller operates in a reduced leakage state having impaired performance capabilities;

detecting an occurrence of an event that indicates a return to normal operating mode;

sending a wake-up signal from the standby micro-controller to a power regulation apparatus configured to selectively operate the main microcontroller in a standard operating state based upon the wake-up signal; and

operating the main micro-controller in the standard operating state having full performance capabilities.

18. The method of claim 17, wherein the main micro-controller writes data to a memory unit in the standby micro-controller to control operation of the standby micro-controller in the standby operating mode.

19. The method of claim 17, further comprising interrupting operation of the standby micro-controller to communicate commands or code to the memory unit by:

sending and holding a reset signal to the standby micro-controller to stop operation of the standby micro-controller;

communicating commands or code to the memory unit within the standby micro-controller; and

releasing the reset signal to resume operation of the standby micro-controller.

20. The method of claim 17, further comprising reading one or more status bits from a status register in the standby micro-controller indicative of an event causing a return to the normal operating mode.