SEMICONDUCTOR STORAGE DEVICE
First Claim
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1. A semiconductor storage device comprising:
- a driver circuit;
a conductive layer over the driver circuit; and
a memory cell array over the conductive layer,wherein the memory cell array comprises a memory cell comprising a transistor, andwherein entirety of the memory cell array overlaps with the conductive layer.
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Abstract
Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.
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Citations
21 Claims
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1. A semiconductor storage device comprising:
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a driver circuit; a conductive layer over the driver circuit; and a memory cell array over the conductive layer, wherein the memory cell array comprises a memory cell comprising a transistor, and wherein entirety of the memory cell array overlaps with the conductive layer. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor storage device comprising:
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a driver circuit; a shielding layer over the driver circuit; and a memory cell array over the shielding layer, wherein the memory cell array comprises a memory cell comprising a transistor, and wherein the shielding layer is configured to shield the driver circuit and the memory cell array from radiation noise generated between the driver circuit and the memory cell array. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A semiconductor storage device comprising:
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a driver circuit; a first insulating film over the driver circuit; a conductive layer over the first insulating film; a second insulating film over the conductive layer; and a memory cell array over the second insulating film, wherein the memory cell array comprises a memory cell comprising a transistor electrically connected to an electrode, wherein a capacitor is formed using a region of the conductive layer as a first electrode, a region of the second insulating film over the region of the conductive layer, and a region of the electrode over the region of the second insulating film as a second electrode, and wherein entirety of the memory cell array overlaps with the conductive layer. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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Specification