Intrinsic channel FET

• US 20130069164A1
• Filed: 09/19/2011
• Published: 03/21/2013
• Est. Priority Date: 09/19/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: ETA Semiconductor, Inc.
• Inventors: Marino, Fabio Alessio, Menegoli, Paolo
• Granted Patent: US 8,803,242 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A novel semiconductor transistor is presented. The semiconductor structure has a MOSFET like structure, with the difference that the device channel is formed in an intrinsic region, so as to effectively decrease the impurity and surface scattering phenomena deriving from a high doping profile typical of conventional MOS devices. Due to the presence of the un-doped channel region, the proposed structure greatly reduces Random Doping Fluctuation (RDF) phenomena decreasing the threshold voltage variation between different devices. In order to control the threshold voltage of the device, a heavily doped poly-silicon or metallic gate is used. However, differently from standard CMOS devices, a high work-function metallic material, or a heavily p-doped poly-silicon layer, is used for a n-channel device and a low work-function metallic material, or heavily n-doped poly-silicon layer, is used for a p-channel FET.

Claims

1. A semiconductor field effect device structure comprising:

a source region and a drain region;

lowly doped channel region between said source and drain regions;

a semiconductor barrier region under said lowly doped channel region;

a dielectric layer extending over at least a portion of said lowly doped channel region;

a gate region extending over said dielectric layer;

wherein said gate region has a work-function equal or greater than the sum between the electron affinity and half energy-gap of said lowly doped channel region, when said semiconductor field effect device is a n-channel device, and

wherein said gate region has a work-function equal or lower than the sum between the electron affinity and half energy-gap of said lowly doped channel region, when said semiconductor field effect device is a p-channel device.

2. The structure of claim 1, wherein said gate region is formed with a material belonging to the group comprising heavily doped semiconductor and metallic materials.

3. The structure of claim 1, wherein said semiconductor barrier region is a highly doped region.

4. The structure of claim 1, wherein the doping of said lowly doped channel region is not uniform.

5. The structure of claim 1, wherein a lowly doped semiconductor region is present under at least one of said source and drain regions.

6. The structure of claim 1, wherein said semiconductor field effect device structure has a bulk multi-gate structure.

7. The structure of claim 1, wherein said source and drain regions are raised with respect to said lowly doped channel region.

8. The structure of claim 1, wherein said lowly doped channel region has a work-function substantially equal to the sum between the electron affinity and half energy-gap.

10. The structure of claim 1, wherein the doping of at least a portion of said lowly doped channel region is unintentional.

12. The structure of claim 1, further comprising a doped layer between said lowly doped channel region and said semiconductor barrier region.

13. The structure of claim 1, wherein a substantially intrinsic semiconductor region is present under at least one of said source and drain regions.

16. The structure of claim 1, wherein said semiconductor barrier region is a highly doped region made of the same semiconductor material of said lowly doped channel region.

18. The structure of claim 1, wherein said lowly doped channel region is formed by means of a semiconductor epitaxial growth process step.

9. A method for forming a semiconductor field effect device structure comprising:

forming a source and a drain region;

forming a dielectric layer by means of deposition or thermal growth process steps, extending over at least a portion of the channel region comprised between said source and drain regions;

forming a gate region by means of deposition of metal or semiconductor material extending over at least a portion of said dielectric layer;

wherein said channel region is a lowly doped region;

wherein a semiconductor barrier region is present under said channel region;

wherein said gate region has a work-function equal or greater than the sum between the electron affinity and half energy-gap of said channel region, when said semiconductor field effect device is a n-channel device, and

wherein said gate region has a work-function equal or lower than the sum between the electron affinity and half energy-gap of said channel region, when said semiconductor field effect device is a p-channel device.

11. The method of claim 9, wherein said semiconductor barrier region is a highly doped region.

14. The method of claim 9, wherein said channel region has the same conductivity type of said source and drain regions.

15. The method of claim 9, wherein said semiconductor field effect device structure has a bulk multi-gate structure.

17. The method of claim 9, wherein said channel region has a work-function substantially equal to the sum between the electron affinity and half energy-gap.

19. A semiconductor field effect device structure comprising:

a source region and a drain region;

a lowly doped channel region between said source and drain regions;

a semiconductor barrier region under said lowly doped channel region;

a dielectric layer extending over at least a portion of said lowly doped channel region;

a gate region extending over said dielectric layer;

wherein said gate region has a work-function substantially equal to the sum between the electron affinity and half energy-gap of said lowly doped channel region.

20. The structure of claim 19, wherein said lowly doped channel region has a work-function substantially equal to the sum between the electron affinity and half energy-gap.