Group III-V Device Structure Having a Selectively Reduced Impurity Concentration

• US 20130069208A1
• Filed: 09/05/2012
• Published: 03/21/2013
• Est. Priority Date: 09/21/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Briere, Michael A.
• Granted Patent: US 8,796,738 B2
• Time in Patent Office: Days
• US Class Current: 257/655
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02455 Group 13/15 materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02634 Homoepitaxy
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Claims

1. A semiconductor structure comprising:

a substrate;

a transition body over said substrate;

a group III-V intermediate body having a bottom surface over said transition body;

a group III-V device layer over a top surface of said group III-V intermediate body;

said group III-V intermediate body having a continuously reduced impurity concentration wherein a higher impurity concentration at said bottom surface is continuously reduced to a lower impurity concentration at said top surface.

2. The semiconductor structure of claim 1, wherein an impurity producing said higher and lower impurity concentrations is a P type impurity.

3. The semiconductor structure of claim 1, wherein said continuously reduced impurity concentration comprises a continuously reduced carbon concentration.

4. The semiconductor structure of claim 1, wherein said continuously reduced impurity concentration includes a plurality of impurity species.

5. The semiconductor structure of claim 1, wherein said group III-V intermediate body comprises a compositionally graded III-Nitride body having a first III-Nitride composition at said bottom surface and a second III-Nitride composition above said bottom surface.

6. The semiconductor structure of claim 1, wherein said group III-V device layer includes at least one of a III-Nitride field-effect transistor (FET) and a III-Nitride high electron mobility transistor (HEMT).

7. The semiconductor structure of claim 1, wherein said transition body includes a group III-V transition structure having a selectively modified impurity concentration such that a bottom surface impurity concentration of said group III-V transition structure is selectively modified to a top surface impurity concentration of said group III-V transition structure.

8. The semiconductor structure of claim 7, wherein said selectively modified impurity concentration is modified in a step-wise fashion from said bottom surface impurity concentration to said top surface impurity concentration.

9. The semiconductor structure of claim 7, wherein said selectively modified impurity concentration rises and falls between said bottom surface impurity concentration and said top surface impurity concentration.

10. A method comprising:

fabricating a transition body over a substrate;

fabricating a group III-V intermediate body having a bottom surface over said transition body;

fabricating a group III-V device layer over a top surface of said group III-V intermediate body;

wherein fabricating said group III-V intermediate body comprises forming a continuously reduced impurity concentration such that a higher impurity concentration at said bottom surface is continuously reduced to a lower impurity concentration at said top surface.

11. The method of claim 10, wherein fabricating said group III-V intermediate body comprises selectively reducing a growth rate of said group III-V intermediate body from a higher growth rate at said bottom surface to a lower growth rate at said top surface.

12. The method of claim 10, wherein fabricating said group III-V intermediate body comprises selectively increasing a growth temperature of said group III-V intermediate body from a lower growth temperature at said bottom surface to a higher growth temperature at said top surface.

13. The method of claim 10, wherein an impurity producing said higher and lower impurity concentrations is a P type impurity.

14. The method of claim 10, wherein forming said continuously reduced impurity concentration comprises forming a continuously reduced carbon concentration.

15. The method of claim 10, wherein said continuously reduced impurity concentration includes a plurality of impurity species.

16. The method of claim 10, wherein said group III-V intermediate body comprises a compositionally graded III-Nitride body having a first III-Nitride composition at said bottom surface and a second III-Nitride composition above said bottom surface.

17. The method of claim 10, wherein said group III-V device layer includes at least one of a III-Nitride field-effect transistor (FET) and a III-Nitride high electron mobility transistor (HEMT).

18. The method of claim 10, wherein fabricating said transition body includes fabricating a group III-V transition structure having a selectively modified impurity concentration such that a bottom surface impurity concentration of said group III-V transition structure is selectively modified to a top surface impurity concentration of said group III-V transition structure.

19. The method of claim 18, wherein said selectively modified impurity concentration is reduced in a step-wise fashion from said bottom surface impurity concentration to said top surface impurity concentration.

20. The method of claim 18, wherein said selectively modified impurity concentration rises and falls between said bottom surface impurity concentration and said top surface impurity concentration.