SEMICONDUCTOR MEMORY DEVICE

• US 20130070533A1
• Filed: 03/06/2012
• Published: 03/21/2013
• Est. Priority Date: 09/21/2011
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: DOZAKA, Toshiaki
• Granted Patent: US 8,953,357 B2
• Time in Patent Office: Days
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 20/34 Source electrode or drain electrode programmed

Abstract

A semiconductor memory device according to an embodiment includes a memory cell array including memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of a word line and a bit line group, the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the bit lines, and an active area serving as a gate of the transistor being continuously formed in arrangement areas of the bit lines of the bit line group and spaces between the bit lines.

Claims

1. A semiconductor memory device comprising:

a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; and

a read circuit configured to read out data from the memory cells through the bit lines,

the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the plurality of bit lines, and

an active area serving as a gate of the transistor being continuously formed in arrangement areas of the plurality of bit lines of the bit line group and spaces between the bit lines, when viewed in a stacking direction that is perpendicular to the row direction and the column direction.

2. The semiconductor memory device according to claim 1,

wherein the bit line group contains three bit lines, and

the memory cell stores data of two bits based on four mutually different connection states including a state in which the source and the drain of the transistor are not electrically connected to any one of the three bit lines belonging to the bit line group and states in which the source and the drain are electrically connected only to specific one of the three bit lines.

3. The semiconductor memory device according to claim 1,

wherein the bit line group contains two bit lines,

the memory cell has three different connection states including a state in which the source and the drain of the transistor are not electrically connected to any one of the two bit lines belonging to the bit line group and states in which the source and the drain are electrically connected only to specific one of the two bit lines, and

the memory cell array stores data of at least three bits by using two memory cells.

4. The semiconductor memory device according to claim 1,

wherein the bit line group contains two bit lines,

the memory cell has two different connection states in which the source and the drain of the transistor are electrically connected only to specific one of the two bit lines, and

the read circuit includes a differential sense amplifier that generates data of one bit by detecting an electric potential difference of the two bit lines of the bit line group.

5. The semiconductor memory device according to claim 1, further comprising:

a bit line precharge/discharge circuit that is disposed between the memory cell array and the read circuit and charges or discharges the plurality of bit lines.

6. The semiconductor memory device according to claim 1, further comprising:

a column multiplexer that is disposed between the memory cell array and the read circuit, selects a certain bit line group from among a plurality of the bit line groups, and outputs a signal of the bit line of the selected bit line group to the read circuit.

7. The semiconductor memory device according to claim 6,

wherein the read circuit includes a precharge/discharge circuit that charges or discharges the bit lines of the bit line group selected by the column multiplexer.

8. The semiconductor memory device according to claim 1,

wherein the memory cell array includes a shield line extending in the column direction between a certain bit line of the memory cell and the bit line of another memory cell adjacent to the certain memory cell.

9. A semiconductor memory device comprising:

a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; and

a read circuit configured to read out data from the memory cells through the bit lines,

the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the plurality of bit lines,

an active area serving as a gate of the transistor being continuously formed in arrangement areas of the plurality of bit lines of the bit line group and spaces between the bit lines, when viewed in a stacking direction that is perpendicular to the row direction and the column direction, and

the memory cell having different layouts of a plurality of layers in accordance with the bit line that is connected to the source or the drain of the transistor.

10. The semiconductor memory device according to claim 9,

wherein the bit line group contains three bit lines, and

the memory cell stores data of two bits based on four different connection states including a state in which the source and the drain of the transistor are not electrically connected to any one of the three bit lines belonging to the bit line group and states in which the source and the drain are electrically connected only to specific one of the three bit lines.

11. The semiconductor memory device according to claim 9,

wherein the bit line group contains two bit lines,

the memory cell has three different connection states including a state in which the source and the drain of the transistor are not electrically connected to any one of the two bit lines belonging to the bit line group and states in which the source and the drain are electrically connected only to specific one of the two bit lines, and

the memory cell array stores data of at least three bits by using two memory cells.

12. The semiconductor memory device according to claim 9,

wherein the bit line group contains two bit lines,

the memory cell has two different connection states in which the source and the drain of the transistor are electrically connected only to specific one of the two bit lines, and

the read circuit includes a differential sense amplifier that generates data of one bit by detecting an electric potential difference of the two bit lines of the bit line group.

13. A semiconductor memory device comprising:

a memory cell array that includes a word line extending in a row direction, a bit line group containing a plurality of bit lines extending in a column direction, and memory cells each formed from a transistor formed over an active area of a well and disposed at intersections of the word line and the bit line group; and

a read circuit configured to read out data from the memory cells through the bit lines,

the memory cell having different connection states including a state in which a source or a drain of the transistor is not electrically connected to any one of the plurality of bit lines belonging to the bit line group and states in which the source or the drain is electrically connected only to a specific one of the plurality of bit lines, and

a gate of the transistor having the row direction as a gate width direction and being continuously formed from one end to the other end of an arrangement area of the bit line group, when viewed in a stacking direction that is perpendicular to the row direction and the column direction.

14. The semiconductor memory device according to claim 13,

wherein the bit line group contains three bit lines, and

the memory cell stores data of two bits based on four different connection states including a state in which the source and the drain of the transistor are not electrically connected to any one of the three bit lines belonging to the bit line group and states in which the source and the drain are electrically connected only to specific one of the three bit lines.

15. The semiconductor memory device according to claim 13,

wherein the bit line group contains two bit lines,

the memory cell has three different connection states including a state in which the source and the drain of the transistor are not electrically connected to any one of the two bit lines belonging to the bit line group and states in which the source and the drain are electrically connected only to specific one of the two bit lines, and

the memory cell array stores data of at least three bits by using two memory cells.

16. The semiconductor memory device according to claim 13,

wherein the bit line group contains two bit lines,

the memory cell has two different connection states in which the source and the drain of the transistor are electrically connected only to specific one of the two bit lines, and

the read circuit includes a differential sense amplifier that generates data of one bit by detecting an electric potential difference of the two bit lines of the bit line group.

17. The semiconductor memory device according to claim 13, further comprising:

a bit line precharge/discharge circuit that is disposed between the memory cell array and the read circuit and charges or discharges the plurality of bit lines.

18. The semiconductor memory device according to claim 13, further comprising:

a column multiplexer that is disposed between the memory cell array and the read circuit, selects a certain bit line group from among a plurality of the bit line groups, and outputs a signal of the bit line of the selected bit line group to the read circuit.

19. The semiconductor memory device according to claim 18,

wherein the read circuit includes a precharge/discharge circuit that charges or discharges the bit lines of the bit line group selected by the column multiplexer.

20. The semiconductor memory device according to claim 13,

wherein a shield line extending in the column direction is formed between a certain bit line of the memory cell and the bit line of another memory cell adjacent to the certain memory cell.