INCREASING THROUGHPUT OF MULTIPLEXED ELECTRICAL BUS IN PIPE-LINED ARCHITECTURE

• US 20130070606A1
• Filed: 09/19/2011
• Published: 03/21/2013
• Est. Priority Date: 09/19/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Asaad, Sameh, Brezzo, Bernard V., Kapur, Mohit
• Granted Patent: US 8,737,233 B2
• Time in Patent Office: Days
• US Class Current: 370/241
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: H04L 12/28 characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] wireless communication networks H04W ; arrangements for dividing the transmission path H04W40/00
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 43/00 Arrangements for monitoring or testing data switching networks

Abstract

Techniques are disclosed for increasing the throughput of a multiplexed electrical bus by exploiting available pipeline stages of a computer or other system. For example, a method for increasing a throughput of an electrical bus that connects at least two devices in a system comprises introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices. Preferably, the signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

Claims

1. A method for increasing a throughput of an electrical bus that connects at least two devices in a system, comprising:

introducing at least one signal hold stage in a signal-receiving one of the two devices, such that a maximum frequency at which the two devices are operated is not limited by a number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices;

wherein each of the two devices comprises a pipelined architecture with one or more pipeline stages for buffering signals, and the signal-transmitting one of the two devices comprises a multiplexer for multiplexing buffered signals from at least one pipeline stage to generate a multiplexed signal that is propagated over the electrical bus, and the signal-receiving one of the two devices comprises a de-multiplexer for de-multiplexing the multiplexed signal received over the electrical bus.

2. The method of claim 1, wherein the number of cycles of an operating frequency of the electrical bus needed for a signal to propagate from a signal-transmitting one of the two devices to the signal-receiving one of the two devices represents a link latency value.

3. The method of claim 2, wherein the at least one signal hold stage introduced in the signal-receiving one of the two devices is a pipeline stage re-allocated from the signal-transmitting one of the two devices.

4. The method of claim 3, wherein re-allocation of the pipeline stage from the signal-transmitting one of the two devices to the signal hold stage of the signal-receiving one of the two devices compensates for the link latency value.

5. The method of claim 1, wherein the system is a field programmable gate array (FPGA) based hardware accelerator that simulates a device under test (DUT), and wherein the two devices are FPGAs which each simulate one or more functions of the DUT.

6. The method of claim 1, wherein the system is a computer system, and wherein the two devices are integrated circuits on at least one printed circuit board of the computer system.

7. The method of claim 1, wherein the system is an integrated circuit, and wherein the two devices are circuit elements of the integrated circuit.

8. A method for increasing a throughput of an electrical bus that connects at least two devices in a system, wherein an operating frequency of the two devices is a function of an operating frequency of the electrical bus divided by a total latency value, and wherein each of the two devices comprises a pipelined architecture with one or more pipeline stages for buffering signals, and the signal-transmitting one of the two devices comprises a multiplexer for multiplexing buffered signals from at least one pipeline stage to generate a multiplexed signal that is propagated over the electrical bus, and the signal-receiving one of the two devices comprises a de-multiplexer for de-multiplexing the multiplexed signal received over the electrical bus, the method comprising:

removing at least one pipeline stage from the signal-transmitting one of the two devices; and

adding at least one signal hold stage in a signal-receiving one of the two devices, such that the operating frequency of the two devices is increased, the total latency value is decreased, and a cycle-accuracy is maintained between the two devices with respect to state prior to the removal and addition steps and a state after the removal and addition steps.

9. The method of claim 8, wherein the system is a field programmable gate array (FPGA) based hardware accelerator that simulates a device under test (DUT), and wherein the two devices are FPGAs which each simulate one or more functions of the DUT.

10. The method of claim 9, wherein the at least one signal hold stage added to the signal-receiving FPGA comprises the at least one pipeline stage removed from the signal-transmitting FPGA.

11. The method of claim 10, wherein the at least one signal hold stage is added to the signal-receiving FPGA between the de-multiplexer and the one or more pipeline stages of the signal-receiving FPGA.

12. The method of claim 8, wherein the removal of the at least one pipeline stage from the signal-transmitting one of the two devices and the addition of the at least one signal hold stage in a signal-receiving one of the two device decreases the total latency value by masking a latency associated with a link between the multiplexer and de-multiplexer.

13. The method of claim 8, wherein:

given that P is a number of signals to be routed from the signal-transmitting one of the two devices to the signal-receiving one of the two devices, C is a number of wires in the electrical bus, M is a multiplex ratio defined as M equals P divided by C, Ft is the operating frequency of the electrical bus, N is a number of cycles of the operating frequency Ft of the electrical bus needed for a signal to propagate from the signal-transmitting one of the two devices to the signal-receiving one of the two devices, B is a number of extra cycles of the operating frequency Ft of the electrical bus needed to compensate for clock phase differences between the signal-transmitting one of the two devices to the signal-receiving one of the two devices, and a maximum frequency Fs at which the two devices are operated is defined as Fs equals Ft divided by the sum of M, N and B, where M, N and B comprise the total latency value;

the removal of the at least one pipeline stage from the signal-transmitting one of the two devices and the addition of the at least one signal hold stage in a signal-receiving one of the two device decreases the total latency value by masking latencies attributable to N and B thereby increasing the maximum operating frequency Fs of the two devices and thus the throughput of the electrical bus.

14. The method of claim 8, wherein the system is a computer system, and wherein the two devices are integrated circuits on at least one printed circuit board of the computer system.

15. The method of claim 8, wherein the system is an integrated circuit, and wherein the two devices are circuit elements of the integrated circuit.