ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS

• US 20130071969A1
• Filed: 09/07/2012
• Published: 03/21/2013
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Vodrahalli, Nagesh, Long, Jon M.
• Granted Patent: US 9,040,348 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/11474 Multilayer masks
• CPC Class Codes: H01L 2224/11845 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/11906 with modification of the same mask
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.

Claims

1. A method of fabricating an electronic assembly, the method comprising:

fabricating a first interconnect, the first interconnect adapted to interconnect a first die to a substrate;

fabricating a second interconnect, the second interconnect adapted to interconnect the first die to a second die; and

assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.

2. The method according to claim 1, wherein the first and second interconnects comprise first and second sets of copper pillars, respectively.

3. The method according to claim 2, wherein fabricating the first and second interconnects further comprises fabricating the first and second sets of copper pillars such that the first set of copper pillars are taller than the second set of copper pillars.

4. The method according to claim 2, wherein fabricating the first interconnect further comprises fabricating the first set of copper pillars on the first die.

5. The method according to claim 4, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the first die.

6. The method according to claim 4, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the second die.

7. The method according to claim 2, wherein fabricating the first interconnect further comprises fabricating the first set of copper pillars on the substrate.

8. The method according to claim 7, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the first die.

9. The method according to claim 7, wherein fabricating the second interconnect further comprises fabricating the second set of copper pillars on the second die.

10. The method according to claim 2, wherein fabricating the second interconnect further comprises coupling analog circuitry fabricated in one of the first and second die to digital circuitry fabricated in the other of the first and second die.

11. The method according to claim 2, wherein fabricating the second interconnect further comprises coupling analog or mixed-signal circuitry fabricated in one of the first and second die to digital circuitry fabricated in the other of the first and second die.

12. The method according to claim 2, wherein fabricating the second interconnect further comprises coupling field programmable gate array (FPGA) circuitry fabricated in one of the first and second die to circuitry fabricated in the other of the first and second die.

13. A method of fabricating an electronic assembly, the method comprising:

fabricating a first interconnect, the first interconnect adapted to interconnect a first die to a substrate;

fabricating a second interconnect, the second interconnect adapted to interconnect the first die to a second die;

fabricating a third interconnect, the third interconnect adapted to interconnect the first die to a third die; and

assembling the first die, the second die, the third die, and the substrate together such that the first die is disposed above the substrate, the second die is disposed below the first die, and the third die is disposed below the first die.

14. The method according to claim 13, wherein assembling the first die, the second die, the third die, and the substrate together further comprises disposing the second die between the first die and the third die.

15. The method according to claim 13, wherein fabricating the first interconnect further comprises fabricating a first set of copper pillars, wherein fabricating the second interconnect further comprises fabricating a second set of copper pillars, and wherein fabricating the third interconnect further comprises fabricating a third set of copper pillars.

16. The method according to claim 15, wherein the first set of copper pillars are taller than the second set of copper pillars.

17. The method according to claim 16, wherein the second set of copper pillars are taller than the third set of copper pillars.

18. A method of fabricating an electronic assembly, the method comprising:

fabricating a first interconnect on a first die;

fabricating a second interconnect on the first die;

interconnecting a second die to the first die using the second interconnect;

interconnecting the first die to a substrate using the first interconnect such that the first die and the second die are disposed above the substrate.

19. The method according to claim 18, wherein interconnecting a second die to the first die using the second interconnect further comprises disposing the second die above the first die.

20. The method according to claim 19, wherein interconnecting the first die to a substrate using the first interconnect such that the first die and the second die are disposed above the substrate further comprises using a flip chip technique.

21. The method according to claim 18, wherein fabricating the first and second interconnects on the first die further comprises:

fabricating a first photoresist layer;

etching selectively the first photoresist layer to fabricate first and second sets of openings; and

depositing copper in the first and second sets of openings.

22. The method according to claim 21, wherein fabricating the first and second interconnects on the first die further comprises performing a first planarization step.

23. The method according to claim 21, wherein fabricating the first and second interconnects on the first die further comprises:

fabricating a second photoresist layer;

etching selectively the second photoresist layer to fabricate a third set of openings; and

depositing copper in the third set of openings.

24. The method according to claim 23, wherein fabricating the first and second interconnects on the first die further comprises performing a second planarization step.

25. The method according to claim 23, wherein fabricating the first and second interconnects on the first die further comprises etching the first and second photoresist layers.