APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NON-VOLATILE MEMORY

• US 20130073786A1
• Filed: 09/16/2011
• Published: 03/21/2013
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Belgal, Hanmant P., Ruby, Paul D., Vogan, Andrew, Guo, Xin, Taub, Mase J., Wu, Ning, Kalastirsky, Ivan
• Granted Patent: US 8,954,650 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem

Abstract

Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.

Claims

1. A method comprising:

identifying whether a block of non-volatile memory (NVM) is a partially programmed block (PPB) based on a read count corresponding to the block of NVM;

comparing the read count with a first threshold when it is identified that the block is a PPB; and

when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold.

2. The method of claim 1 further comprises:

incrementing the read count when the read count is less than the first threshold; and

classifying the PPB as a fully programmed block (FPB) when the read count is greater than the first threshold,

3. The method of claim 2, wherein classifying the PPB as a FPB comprises closing write access to the PPB.

4. The method of claim 1 further comprises:

incrementing the read count when the read count is less than the second threshold; and

relocating the block to a new location when the read count is greater than the second threshold.

5. The method of claim 4, wherein relocating the block comprises:

moving data in the block to a new block in another location in the NVM;

erasing the data in the block of NVM;

resetting the read count corresponding to the erased block of NVM; and

resetting the read count corresponding to the new block of the NVM.

6. The method of claim 5 further comprises:

allowing new data to be written to the block in response to resetting the read count corresponding to the erased block of NVM.

7. The method of claim 1, wherein the first and second thresholds are programmable.

8. The method of claim 1, wherein the first and second thresholds are adjusted according to program erase cycles associated with the block of NVM.

9. The method of claim 1 further comprises:

storing, in the NVM, the read count of the block in response to identifying a power down event.

10. The method of claim 1 further comprises:

periodically storing the read count of the block in the NVM while the NVM is powered on.

11. The method of claim 1, wherein the NVM is a NAND flash memory.

12. A memory controller comprising:

a logic unit to identify whether a block of non-volatile memory (NVM) is a partially programmed block (PPB) based on a read count corresponding to the block of NVM; and

a comparator to compare the read count with a first threshold when it is identified that the block is a PPB, wherein the comparator to compare the read count with a second threshold when it is identified otherwise, wherein the first threshold is smaller than the second threshold.

13. The memory controller of claim 12 further comprises:

a third unit to;

increment the read count when the read count is less than the first threshold; and

increment the read count when the read count is less than the second threshold; and

a fourth logic to classify the PPB as a fully programmed block (FPB) when the read count is greater than the first threshold, wherein classifying the PPB as a FPB comprises closing write access to the PPB.

14. The memory controller of claim 13 further comprises a fifth logic to relocate the block to a new location when the read count is greater than the second threshold.

15. The memory controller of claim 14, wherein the fifth logic to relocate the block by executing a process comprising:

moving data in the block to a new block in another location in the NVM;

erasing the data in the block of NVM;

resetting the read count corresponding to the erased block of NVM; and

resetting the read count corresponding to the new block of the NVM.

16. The memory controller of claim 15 further comprises logic to allow new data to be written to the block in response to resetting the read count corresponding to the erased block of NVM.

17. The memory controller of claim 12, wherein the first and second thresholds are programmable, and wherein the first and second thresholds are adjustable according to program erase cycles associated with the block of NVM.

18. The memory controller of claim 12 further comprises a logic unit to:

store, in the NVM, the read count of the block in response to identifying a power down event; and

periodically store the read count of the block in the NVM while the NVM is powered on.

19. The memory controller of claim 12, wherein the NVM is a NAND flash memory.

20. A system comprising:

a solid state drive (SSD) comprising a controller and a non-volatile memory (NVM), wherein the controller is operable to;

identify whether a block of NVM is a partially programmed block (PPB) based on a read count corresponding to the block of NVM; and

compare the read count with a first threshold when it is identified that the block is a PPB; and

compare the read count with a second threshold when identified otherwise, wherein the first threshold is smaller than the second threshold; and

a display unit which is operable to display contents from the SSD.

21. The system of claim 20, wherein the controller is operable to:

increment the read count when the read count is less than the first threshold; and

increment the read count when the read count is less than the second threshold; and

classify the PPB as a fully programmed block (FPB) when the read count is greater than the first threshold, wherein classifying the PPB as a FPB comprises closing write access to the PPB.

22. The system of claim 20, wherein the controller is operable to relocate the block to a new location when the read count is greater than the second threshold.

23. The system of claim 20, wherein the controller is operable to:

move data in die block to a new block in another location in the NVM;

erase the data in the block of NVM;

reset the read count corresponding to the erased block of NVM; and

reset the read count corresponding to the new block of the NVM.

24. The system of claim 23, wherein the controller is operable to allow new data to be written to the block in response to resetting the read count corresponding to the erased block of NVM.

25. The system of claim 20, wherein the first and second thresholds are programmable, and wherein the first and second thresholds are adjustable according to program erase cycles associated with the block of NVM.

26. The system of claim 20, wherein the controller is operable to:

store, in the NVM, the read count of the block in response to identifying a power down event; and

periodically store the read count of the block in the NVM while the NVM is powered on.

27. The system of claim 20, wherein the NVM is a NAND flash memory.

28. An article of manufacture including a machine readable storage medium having processor executable instructions that when executed cause a processor to perform a method comprising:

identifying whether a block of non-volatile memory (NVM) is a partially programmed block (PPB) based on a read count corresponding to the block of NVM;

comparing the read count with a first threshold when it is identified that the block is a PPB; and

when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold.

29. The article of manufacture of claim 28, wherein the machine readable storage medium includes further processor executable instructions that when executed cause the processor to perform a method comprising:

incrementing the read count when the read count is less than the first threshold; and

classifying the PPB as a fully programmed block (FPB) when the read count is greater than the first threshold, wherein classifying the PPB as a FPB comprises closing write access to the PPB.

30. The article of manufacture of claim 28, wherein the machine readable storage medium includes further processor executable instructions that when executed cause the processor to perform a method comprising:

incrementing the read count when the read count is less than the second threshold; and

relocating the block to a new location when the read count is greater than the second threshold.