MEMORY DEVICE

• US 20130073793A1
• Filed: 03/20/2012
• Published: 03/21/2013
• Est. Priority Date: 09/16/2011
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Misao Hasegawa, Osamu Yamagishi
• Inventors: Shiraishi, Atsushi, YAMAGISHI, Osamu, Hasegawa, Misao
• Granted Patent: US 8,909,854 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence

Abstract

According to one embodiment, a memory device includes a nonvolatile memory which stores data in units of a write unit includes cells, and a controller which controls the memory and partitions memory space of the memory. In response to a request to write write-data to the memory from a host, the controller requests the host to transmit a segment of the write-data with a specified size. The write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit. Before completion of processing a first command which requests access to a first partition, the controller accepts a second command which requests access to a second partition.

Claims

1. A memory device comprising:

a nonvolatile memory which stores data in units of a write unit comprising cells; and

a controller which

controls the memory,

partitions memory space of the memory,

in response to a request to write write-data to the memory from a host device, requests the host device to transmit a segment of the write-data with a specified size, wherein the write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit, and

before completion of processing a first command which requests access to a first partition, accepts a second command which requests access to a second partition.

2. The device of claim 1, wherein

the controller executes parts of processing requested by the first command and parts of processing requested by the second command in turn when it receives the second command before processing of the first command is completed.

3. The device of claim 2, wherein

when the controller receives, before completion of processing requested by one or more preceding commands requesting access to one or more partitions, a succeeding command requesting access to another partition,

the controller executes parts of processing requested by each of the preceding commands and parts of processing requested by the succeeding command in turn equally for each of the preceding commands and the succeeding command.

4. The device of claim 1, wherein

when the controller receives the second command before processing of the first command is completed, the controller suspends processing requested by one of the first and second commands which requests access to one of the first and second partitions with a lower priority and completes processing requested by the other one of the first and second commands.

5. The device of claim 1, wherein

the controller takes one of a first mode and a second mode,

the controller in the first mode accepts a command requesting access to the second partition before completion of processing requested by another command requesting access to the first partition, and

the controller in the second mode refuses a command requesting access to the second partition before completion of processing requested by another command requesting access to the first partition.

6. The device of claim 1, wherein

the additional data comprises at least one of management data for a corresponding write-data segment and an error correcting code.

7. The device of claim 6, wherein

the controller comprises an error correcting code circuit which generates the error correcting code, and

the error correcting code circuit generates error correcting codes in units of a correction unit which is a segment of received data.

8. The device of claim 7, wherein

the remaining portion of the write unit without a set of the write-data segment and corresponding management data is smaller than a set of the correction unit and the additional data for the correction unit.

9. The device of claim 1, wherein

the write-data segment has a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit.

10. The device of claim 1, wherein

the memory device comprises a UFS memory device.

11. The device of claim 1, wherein

the memory device comprises a first logical unit and a second logical unit which comprises respective portions of function of the controller and respective portions of the memory space, and

the first and second logical units write data to the respective portions of the memory space and transmit respective requests to transmit the write-data segment, separately.

12. A memory device comprising:

a nonvolatile memory which stores data in units of a write unit comprising cells; and

a controller which

controls the memory,

partitions memory space of the memory,

in response to a request to write write-data to the memory from a host device, requests the host device to transmit a segment of the write-data with a specified size, wherein the write-data segment has a size to allow the write data-segment written in the write unit to fit the end of the write data unit, and

before completion of processing a first command which requests access to a first partition, accepts a second command which requests access to a second partition.

13. The device of claim 12, wherein

the controller executes parts of processing requested by the first command and parts of processing requested by the second command in turn when it receives the second command before processing of the first command is completed.

14. The device of claim 13, wherein

when the controller receives, before completion of processing requested by one or more preceding commands requesting access to one or more partitions, a succeeding command requesting access to another partition,

the controller executes parts of processing requested by each of the preceding commands and parts of processing requested by the succeeding command in turn equally for each of the preceding commands and the succeeding command.

15. The device of claim 12, wherein

when the controller receives the second command before processing of the first command is completed, the controller suspends processing requested by one of the first and second commands which requests access to one of the first and second partitions with a lower priority and completes processing requested by the other one of the first and second commands.

16. The device of claim 12, wherein

the controller takes one of a first mode and a second mode,

the controller in the first mode accepts a command requesting access to the second partition before completion of processing requested by another command requesting access to the first partition, and

the controller in the second mode refuses a command requesting access to the second partition before completion of processing requested by another command requesting access to the first partition.