ADAPTIVE MAPPING OF LOGICAL ADDRESSES TO MEMORY DEVICES IN SOLID STATE DRIVES

• US 20130073822A1
• Filed: 06/28/2012
• Published: 03/21/2013
• Est. Priority Date: 09/20/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sandel, Eran, Golov, Oren
• Granted Patent: US 9,417,803 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/3433 for load management allocation of a server based on load conditions G06F9/505; load rebalancing G06F9/5083; redistributing the load in a network by a load balancer H04L67/1029
• CPC Class Codes: G06F 11/3485 for I/O devices
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method for data storage includes receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units. Respective estimates of a performance characteristic are obtained for the multiple memory units. A mapping, which maps the logical addresses to respective physical storage locations in the multiple memory units, is adapted based on the estimates so as to balance the performance characteristic across the memory units. The data items are stored in the physical storage locations in accordance with the adapted mapping.

Claims

1. A method for data storage, comprising:

receiving data items associated with respective logical addresses for storage in a memory that includes multiple memory units;

obtaining respective estimates of a performance characteristic for the multiple memory units;

based on the estimates, adapting a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, so as to balance the performance characteristic across the memory units; and

storing the data items in the physical storage locations in accordance with the adapted mapping.

2. The method according to claim 1, wherein adapting the mapping comprises modifying a total number of the logical addresses that are mapped to a given memory unit.

3. The method according to claim 1, wherein storing the data items comprises distributing the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units, and wherein adapting the mapping comprises modifying one or more of the weights.

4. The method according to claim 3, wherein modifying the weights comprises assigning to a given memory unit different first and second weights for respective different first and second types of memory access commands.

5. The method according to claim 1, wherein obtaining the estimates comprises evaluating the performance characteristic for the multiple memory units during production of the memory or the memory units.

6. The method according to claim 1, wherein obtaining the estimates comprises evaluating the performance characteristic for the multiple memory units while the memory is operating in a host system.

7. The method according to claim 1, wherein adapting the mapping comprises initially storing the data items in the memory in accordance with an initial setting of the mapping, and subsequently adapting the mapping and copying one or more of the data items so as to store the data items in the memory in accordance with the adapted mapping.

8. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective count of memory blocks in the memory unit that are available for programming.

9. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective count of faulty memory blocks in the memory unit.

10. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective time duration of a memory access command applied to the memory unit.

11. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective read error performance of the memory unit.

12. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective endurance of the memory unit.

13. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective frequency of access to data stored in the memory unit.

14. The method according to claim 1, wherein the performance characteristic for each memory unit is indicative of a respective count of memory access commands pending for execution in the memory unit.

15. A data storage apparatus, comprising:

an interface, which is configured to communicate with a memory that includes multiple memory units; and

a processor, which is configured to receive data items associated with respective logical addresses for storage in the memory, to obtain respective estimates of a performance characteristic for the multiple memory units, to adapt, based on the estimates, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, so as to balance the performance characteristic across the memory units, and to store the data items in the physical storage locations in accordance with the adapted mapping.

16. The apparatus according to claim 15, wherein the processor is configured to adapt the mapping by modifying a total number of the logical addresses that are mapped to a given memory unit.

17. The apparatus according to claim 15, wherein the processor is configured to distribute the data items among the memory units in accordance with a weighted Round-Robin scheduling scheme that assigns respective weights to the memory units, and to adapt the mapping by modifying one or more of the weights.

18. The apparatus according to claim 17, wherein the processor is configured to assign to a given memory unit different first and second weights for respective different first and second types of memory access commands.

19. The apparatus according to claim 15, wherein the processor is configured to accept an evaluation of the performance characteristic for the multiple memory units, which was performed during production of the memory or the memory units.

20. The apparatus according to claim 15, wherein the processor is configured to evaluate the performance characteristic for the multiple memory units while the memory is operating in a host system.

21. The apparatus according to claim 15, wherein the processor is configured to initially store the data items in the memory in accordance with an initial setting of the mapping, and to subsequently adapt the mapping and copy one or more of the data items so as to store the data items in the memory in accordance with the adapted mapping.

22. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective count of memory blocks in the memory unit that are available for programming.

23. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective count of faulty memory blocks in the memory unit.

24. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective time duration of a memory access command applied to the memory unit.

25. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective read error performance of the memory unit.

26. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective endurance of the memory unit.

27. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective frequency of access to data stored in the memory unit.

28. The apparatus according to claim 15, wherein the performance characteristic for each memory unit is indicative of a respective count of memory access commands pending for execution in the memory unit.

29. A data storage apparatus, comprising:

a memory comprising multiple memory units; and

a processor, which is configured to receive data items associated with respective logical addresses for storage in the memory, to obtain respective estimates of a performance characteristic for the multiple memory units, to adapt, based on the estimates, a mapping that maps the logical addresses to respective physical storage locations in the multiple memory units, so as to balance the performance characteristic across the memory units, and to store the data items in the physical storage locations in accordance with the adapted mapping.