APPARATUS AND METHODS FOR AN INTERCONNECT POWER MANAGER

• US 20130073878A1
• Filed: 03/29/2012
• Published: 03/21/2013
• Est. Priority Date: 09/19/2011
• Status: Active Grant

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Jayasimha, Doddaballapur N., Wingard, Drew E., Hamilton, Stephen W.
• Granted Patent: US 8,868,941 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN.

Claims

1. An apparatus, comprising:

an interconnect-power-manager that has hardware circuitry and signaling ports configured to cooperate and communicate with an integrated-circuit-system-power-manager as well as with different agents within an interconnect network for the integrated circuit, where the interconnect network is partitioned into multiple power domains, and the interconnect-power-manager has the hardware circuitry integrated into the interconnect network to manage a quiescent state for all components in each power domain in the interconnect network when a routing pathway for transactions in the interconnect network spans across one or more power domain boundaries and causes interdependencies of power domains within the interconnect network other than the locations of the power domains containing an initiator agent generating a new transaction and a final target agent of the new transaction, where one or more initiator cores each couple to their own corresponding initiator agent, and one or more target cores each couple to their own corresponding target agent, and those different agents have their power state managed by the integrated-circuit-system-power-manager, which is separate than the interconnect-power-manager managing the multiple power domains of the interconnect network, where the integrated-circuit-system-power-manager is configured to cooperate and communicate with the interconnect-power-manager

     1) to quiesce,

     2) to wake up, and

     3) any combination of the two, one or more of the multiple power domains within the interconnect network, where each power domain is separately controllable from other power domains in the interconnect network by the interconnect-power-manager.

2. The apparatus of claim 1, where the interconnect network is used to communicate and route transactions between the initiator IP cores and the target IP cores in the integrated circuit, and the integrated-circuit-system-power-manager controls the multiple power domains of the interconnect network via its cooperation with the interconnect-power-manager as well those containing the initiator and target cores themselves, where the integrated-circuit-system-power-manager is external to the interconnect network, and where each power domain is separately controllable from other power domains in the interconnect network allows for flexible power management control by the external integrated-circuit-system-power-manager cooperating and interfacing with the interconnect-power-manager.

3. The apparatus of claim 1, where one or more initiator agents in the interconnect network each has its own status registers for one or more target agents in each power domain that the initiator agent connects to, and combinational logic that is used to represent the power domains that the routers belong to in the routing pathway between the initiator agent and the final target agent within the interconnect network to indicate a power mode state regarding each power domain this initiator agent has connectivity with, and where the combinational logic and status registers in cooperation with the interconnect-power-manager track and control a quiescent state for all components in each power domain when the routing pathway in the interconnect network from the initiator agent to the final destination target agent spans across the one or more power domain boundaries within the interconnect.

4. The apparatus of claim 1, where the interconnect-power-manager is configured to wake up a quiesced power domain upon an arrival of the new transaction needing to traverse the routing pathway in the interconnect network from the initiator agent to the final destination target agent that spans across that power domain in the quiesced power state, where the interconnect-power-manager in cooperation with a configuration register provides two or more mechanisms selectable by a designer at run time to wake up any of the quiesced power domains that the transaction needs to complete the routing pathway from the initiator agent to the final target agent destination, and where the two or more mechanisms include 1) the quiesced power domains can be either awakened “

all at once”

with the new transaction waiting at the initiator core during a wakeup period or

     2) each quiesced power domain can be awakened on demand as the new transaction progresses from the initiator agent to the final target agent destination through the interconnect network.

5. The apparatus of claim 1, where two or more power domains in the interconnect network contain a designer identified and selected set of interconnect components, including any of routers, arbitration units, initiator agents, and target agents, which the designer identifies in a table that should be quiesced or awakened together in that power domain and the components represented in the table can be set by the designer of the system at run time to in part to allow a more flexible partitioning of clock and power domains in later stages of the chip design than allowed with earlier technologies.

6. The apparatus of claim 1, further comprising:

two or more initiator agents located within the interconnect network, where the hardware circuitry in the interconnect-power-manager and each of the initiator agents is configured to track a quiescent state of components and routing interdependencies of other power domains in the interconnect network needed to route a transaction between that initiator agent to other target and initiator cores connected to that initiator agent on a per power domain basis.

7. The apparatus of claim 1, where the hardware circuitry including status registers within the interconnect-power-manager handles the quiescing and waking up of the components within the interconnect network in the power domains, and the interconnect-power-manager also has signaling interfaces with the integrated-circuit-system-power-manager per power domain in order to coordinate power domain state transitions of each power domain separately from other power domains in the interconnect network.

8. The apparatus of claim 1, where the hardware circuitry in the interconnect-power-manager is configured to respond to an incoming transaction which cannot establish a path through the multiple power domains within the interconnect network from the initiator core to the final destination target core because one or more components in the path are quiesced, where the hardware circuitry causes the transaction to either be blocked at the initiator agent or errored out until a wakeup signal is enabled to wakeup the relevant power domains in the interconnect network including any intervening power domains in the interconnect network.

9. The apparatus of claim 1, where the hardware circuitry in the interconnect-power-manager includes multiple power domain controllers each with its own state machine to control a quiescing and waking up of the components within that power domain, and one power domain controller per power domain in the interconnect network, and one or more status registers located with each initiator agent that indicate a quiesce power state of each target agent and the quiesce power state of routers along the path from the initiator agent to the final target agent that have connectivity through routing pathways in the interconnect network with that initiator agent.

10. The apparatus of claim 1, where each initiator agent in the interconnect network has a tracking mechanism to track a quiesce state for each external power domain that this agent has connectivity with through routing pathways in the interconnect network, and also contains logic to know the power state of each interconnect network component internal to the power domain containing that initiator agent in order to know which particular interconnect network components need to be requested to be awakened.

11. The apparatus of claim 1, where logic and a corresponding signaling interface are incorporated into each initiator agent structure to interface with the integrated-circuit-system-power-manager and to achieve when 1) a power domain is to be quiesced, 2) outstanding transactions are to be drained, and 3) additional transactions which use components belonging to the power domain are to be fenced at that initiator agent.

12. The apparatus of claim 1, where an appropriate subset of a connectivity matrix used in an initiator agent is configurable by a designer of the integrated circuit to indicate all of the target IP cores this initiator agent connects to and its routing pathway as well as an address map of the target and IP cores coupling to the interconnect network, where the initiator agent locally stores its appropriate subset of the connectivity matrix.

13. The apparatus of claim 1, where the initiator agent has logic to monitor an outstanding status of each transaction received by that initiator agent, where the interconnect-power-manager is configured for power management flows to quiesce target agents a) by ensuring that all outstanding transactions to it from an initiator agent are returned b) by an initiator agent not generating new transactions to the target agent, once the quiesce request is received at the initiator agent, and c) by any combination of the two above.

14. The apparatus of claim 1, where the interconnect-power-manager has a) two or more power domain controllers to control a quiescing and waking up of the components within that power domain, one power domain controller for each power domain, an external interface with the integrated-circuit-system-power-manager and logic to support the external interface, and an internal interface for each power domain as well as b) the appropriate logic to broadcast the status of whether a request or response transaction has completed its traversing across the interconnect network, where the interconnect-power-manager includes the hardware circuitry integrated with the interconnect network including the two or more power domain controllers, interfaces, and logic that are configured to quiesce and wakeup power domains within the interconnect network by communicating with hardware in the different agents in the multiple domains within the interconnect network.

15. The apparatus of claim 1, where the hardware circuitry in the interconnect-power-manager includes a state machine in each power domain controller in the interconnect-power-manager, where each state machine is configured to ensure that the quiescence flow begins only when all components in the power domain associated with that power domain controller are awake as indicated by status registers and a wakeup flow begins only when all components in the domain are quiesced as indicated by the status registers.

16. The apparatus of claim 1, where the hardware circuitry in the interconnect-power-manager includes two or more power domain controllers and each power domain controller has a state machine configured to send a signal to logic in each initiator agent to ensure that the quiescence flow begins only when all outstanding transactions are retired that are routed to or through components in the domain and to ensure that wake up of components in a power domain occurs when a transaction needs to traverse through that power domain, and where one or more status registers located with each initiator agent indicate a quiesce power state of the power domains within the interconnect network that have connectivity through routing pathways in the interconnect network with that initiator agent.

17. A machine-readable medium having data and instructions stored thereon, which, when executed by a machine, cause the machine to generate a representation of the apparatus of claim 1, wherein the machine-readable medium stores an Electronic Design Automation (EDA) toolset used in a System-on-a-Chip design process that has the data and instructions to generate the representations of the apparatus.

18. A method to manage power in an integrated circuit;

comprising;

cooperating and communicating signals between an interconnect-power-manager with an integrated-circuit-system-power-manager in an integrated-circuit, where the interconnect network is partitioned into multiple power domains and has hardware circuitry integrated into the interconnect network to manage a quiescent state for all components in each power domain in the interconnect network when a routing pathway for transactions in the interconnect network spans across one or more power domain boundaries and causes interdependencies of power domains within the interconnect network other than where the power domains of an initiator agent of a new transaction and final target agent of the new transaction are located within;

managing a power state of one or more initiator cores coupled to their own corresponding initiator agent and one or more target cores coupled to their own corresponding target agent have their power state with the integrated-circuit-system-power-manager, which is separate than the interconnect-power-manager; and

where the integrated-circuit-system-power-manager is configured to cooperate and communicate with the interconnect-power-manager to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the interconnect network, where each power domain is separately controllable from other power domains in the interconnect network by the interconnect-power-manager.

19. The method of claim 18, further comprising:

using status registers in each initiator agent in the interconnect network for one or more target agents in each power domain that the initiator agent connects to and using combinational logic to represent the power domains that the routers belong to in the routing pathway between the initiator agent and the final target agent within the interconnect network to indicate a power mode state regarding each power domain this initiator agent has connectivity with; and

tracking and controlling a quiescent state for all components in each power domain when the routing pathway in the interconnect network from the initiator agent to the final destination target agent spans across the one or more power domain boundaries within the interconnect.

20. The method of claim 19, further comprising:

monitoring an outstanding status of each transaction received by a first initiator agent, where the interconnect-power-manager is configured for power management flows to quiesce target agents a) by ensuring that all outstanding transactions to it from the first initiator agent are returned b) by the first initiator agent not generating new transactions to the target agent, once the quiesce request is received at the first initiator agent, and c) by any combination of the two above.

21. An apparatus, comprising:

an interconnect-power-manager that has hardware circuitry and signaling ports configured to cooperate and communicate with an integrated-circuit-system-power-manager for the integrated circuit, where the interconnect network is partitioned into multiple power domains, and the interconnect-power-manager has the hardware circuitry integrated into the interconnect network to manage a quiescent state for all interconnect network components in each power domain, where the interconnect-power-manager is configured to cooperate with the integrated-circuit-system-power-manager to wake up two or more quiesced power domains in parallel upon an arrival of the new transaction needing to traverse the routing pathway in the interconnect network from an initiator agent to a final destination target agent, and the initiator agent is configured to cause the new transaction to wait at the initiator core during a wakeup period of the two or more power domains.

22. An apparatus, comprising:

an interconnect-power-manager that has hardware circuitry and signaling ports configured to cooperate and communicate with an integrated-circuit-system-power-manager as well as with multiple initiator agents within an interconnect network for the integrated circuit, where the interconnect network is partitioned into multiple power domains, and the interconnect-power-manager has the hardware circuitry integrated into the interconnect network to manage a quiescent state for all components in the interconnect network in each power domain when a routing pathway for transactions in the interconnect network spans across one or more power domain boundaries and causes interdependencies of power domains within the interconnect network other than the locations of the power domains containing a first initiator agent generating a new transaction and a final target agent of the new transaction, where the integrated-circuit-system-power-manager controls power management within the interconnect network by monitoring only status registers located within each of the initiator agents, where the status registers indicate a composite of the quiescent state for all interconnect network components including initiator agents, target agents, and routers in each power domain in the interconnect network that have connectivity to that initiator agent.

23. An interconnect-power-manager that has hardware circuitry and signaling ports configured to cooperate and communicate with an integrated-circuit-system-power-manager for the integrated circuit, where the interconnect network is partitioned into multiple power domains, and the interconnect-power-manager has the hardware circuitry integrated into the interconnect network to manage a quiescent state for all interconnect network components in each power domain when a routing pathway for transactions in the interconnect network spans across one or more power domain boundaries, where the interconnect-power-manager is configured to control transaction activity management within the multiple power domains within the interconnect network by sending one or more signals to quiesce or awaken interconnect network components contained within these multiple power domains, and the integrated-circuit-system-power-manager is configured to turn power on and off to the multiple power domains within the interconnect network, where the integrated-circuit-system-power-manager turns off power to a given power domain when all of the components within that given power domain in the integrated circuit are quiesced, where the interconnect-power-manager decouples transaction activity management in the multiple power domains from the integrated-circuit-system-power-manager'"'"'s control of power management in order to allow interconnect network components to be contained in two or more power domains along with at least one of 1) an initiator Intellectual Property core, 2) a target IP core, and 3) any combination of both within each of those two or more power domains.