Dynamic Power Optimization For Computing Devices

• US 20130073883A1
• Filed: 11/23/2011
• Published: 03/21/2013
• Est. Priority Date: 09/20/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Vick, Christopher A., Wright, Gregory M.
• Granted Patent: US 8,799,693 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In the various aspects, virtualization techniques may be used to reduce the amount of power consumed by execution of applications by power-optimizing the code prior to execution. A dynamic binary translator operating at the machine layer may use a power consumption model to identify code segments that can benefit from optimization and to perform an instruction-sequence to instruction-sequence translation of object code to generate power-optimized object code. Execution hardware may be instrumented with additional circuitry to measure the power consumption characteristics of executing code. The power consumption models may be updated and object code may be regenerated based on the measured the power consumption characteristics of previously executed code. In an aspect, power optimization may be accomplished when the computing device is connected to a battery charger.

Claims

1. A method for optimizing object code for power savings during execution on a computing device, comprising:

receiving compiled binary object code in a computing device'"'"'s system software;

analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;

performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and

executing the power optimized object code on a processor of the computing device.

2. The method of claim 1, wherein the system software which receives the compiled binary object code is one of a system virtual machine or a hypervisor.

3. The method of claim 1, wherein the system software which receives the compiled binary object code is an operating system.

4. The method of claim 1, wherein performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises translating a first instruction set architecture into a second instruction set architecture.

5. The method of claim 4, wherein the first instruction set architecture is the same instruction set architecture as the second instruction set architecture.

6. The method of claim 1, wherein analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings comprises determining whether there are alternative operations that achieve the same results as the identified object code operations, and

wherein performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises replacing, during translation, the identified object code operations with the alternative operations.

7. The method of claim 1, further comprising sensing a connection to a new power source, wherein performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code is performed when connection to the new power source is sensed.

8. The method of claim 1, wherein analyzing the received object code comprises using a power consumption model to identify segments of object code that can be optimized for power efficiency.

9. The method of claim 8, further comprising:

measuring an amount of power consumed in the execution of segments of power optimized object code;

comparing the measured amount of power consumed to predictions of the power consumption model; and

modifying the power consumption model based on a result of the comparison.

10. A computing device configured to optimize object code during execution for improved power savings, comprising:

means for receiving compiled binary object code in system software;

means for analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;

means for performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and

means for executing the power optimized object code on a processor of the computing device.

11. The computing device of claim 10, wherein means for receiving compiled binary object code in system software comprises means receiving the compiled binary object code in one of a system virtual machine or a hypervisor.

12. The computing device of claim 10, wherein means for receiving compiled binary object code in system software comprises means receiving the compiled binary object code in an operating system.

13. The computing device of claim 10, wherein means for performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises means for translating a first instruction set architecture into a second instruction set architecture.

14. The computing device of claim 13, wherein means for translating a first instruction set architecture into a second instruction set architecture comprises means for translating the first instruction set architecture into an instruction set architecture that is the same as the second instruction set architecture.

15. The computing device of claim 10, wherein:

means for analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings comprises means for determining whether there are alternative operations that achieve the same results as the identified object code operations; and

means for performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises means for replacing, during translation, the identified object code operations with the alternative operations.

16. The computing device of claim 10, further comprising means for sensing a connection to a new power source, wherein means for performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises means for translating the received code to generate power optimized object code when connection to the new power source is sensed.

17. The computing device of claim 10, wherein means for analyzing the received object code comprises means for using a power consumption model to identify segments of object code that can be optimized for power efficiency.

18. The computing device of claim 10, further comprising:

means for measuring an amount of power consumed in the execution of segments of power optimized object code;

means for comparing the measured amount of power consumed to predictions of the power consumption model; and

means for modifying the power consumption model based on a result of the comparison.

19. A computing device, comprising:

a memory; and

one or more processors coupled to the memory, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations comprising;

receiving compiled binary object code in system software;

analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;

performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and

executing the power optimized object code.

20. The computing device of claim 19, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations such that receiving compiled binary object code in system software comprises receiving the compiled binary object code in one of a system virtual machine or a hypervisor.

21. The computing device of claim 19, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations such that receiving compiled binary object code in system software comprises receiving the compiled binary object code in an operating system.

22. The computing device of claim 19, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations such that performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises translating a first instruction set architecture into a second instruction set architecture.

23. The computing device of claim 22, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations such that the first instruction set architecture is the same as the second instruction set architecture.

24. The computing device of claim 19, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations such that:

analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings comprises determining whether there are alternative operations that achieve the same results as the identified object code operations; and

performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises replacing, during translation, the identified object code operations with the alternative operations.

25. The computing device of claim 19, wherein:

the one or more processors are configured with processor-executable instructions so the computing device performs operations further comprising sensing a connection to a new power source; and

the one or more processors are configured with processor-executable instructions so the computing device performs operations such that performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code is performed when connection to the new power source is sensed.

26. The computing device of claim 19, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations such that analyzing the received object code comprises using a power consumption model to identify segments of object code that can be optimized for power efficiency.

27. The computing device of claim 26, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations further comprising:

measuring an amount of power consumed in the execution of segments of power optimized object code;

comparing the measured amount of power consumed to predictions of the power consumption model; and

modifying the power consumption model based on a result of the comparison.

28. A non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations for optimizing object code for power savings during execution on a computing device, the operations comprising:

receiving compiled binary object code in system software;

analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;

performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and

executing the power optimized object code on a processor of the computing device.

29. The non-transitory processor-readable storage medium of claim 28, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that receiving compiled binary object code in system software comprises receiving the compiled binary object code in one of a system virtual machine or a hypervisor.

30. The non-transitory processor-readable storage medium of claim 28, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that receiving compiled binary object code in system software comprises receiving the compiled binary object code in an operating system.

31. The non-transitory processor-readable storage medium of claim 28, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises translating a first instruction set architecture into a second instruction set architecture.

32. The non-transitory processor-readable storage medium of claim 31, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that the first instruction set architecture is the same as the second instruction set architecture.

33. The non-transitory processor-readable storage medium of claim 28, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that:

analyzing the received object code in a dynamic binary translator process operating at the machine layer to identify code segments that can be optimized for power savings comprises determining whether there are alternative operations that achieve the same results as the identified object code operations; and

performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises replacing, during translation, the identified object code operations with the alternative operations.

34. The non-transitory processor-readable storage medium of claim 28, wherein:

the stored processor-executable software instructions are configured to cause a processor to perform operations comprising sensing a connection to a new power source; and

the stored processor-executable software instructions are further configured to cause a processor to perform operations such that performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code is performed when connection to the new power source is sensed.

35. The non-transitory processor-readable storage medium of claim 28, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations such that analyzing the received object code comprises using a power consumption model to identify segments of object code that can be optimized for power efficiency.

36. The non-transitory processor-readable storage medium of claim 35, wherein the stored processor-executable software instructions are configured to cause a processor to perform operations further comprising:

measuring an amount of power consumed in the execution of segments of power optimized object code;

comparing the measured amount of power consumed to predictions of the power consumption model; and

modifying the power consumption model based on a result of the comparison.

37. A system on chip, comprising:

a memory; and

one or more cores coupled to the memory, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations comprising;

receiving in an operating system compiled binary object code;

analyzing the received object code in a dynamic binary translator process operating at the machine layer to identify code segments that can be optimized for power savings;

performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and

executing the power optimized object code.

38. The system on chip of claim 37, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations such that performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises translating a first instruction set architecture into a second instruction set architecture.

39. The system on chip of claim 38, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations such that the first instruction set architecture is the same as the second instruction set architecture.

40. The system on chip of claim 37, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations such that:

analyzing the received object code in a dynamic binary translator process operating at the machine layer to identify code segments that can be optimized for power savings comprises determining whether there are alternative operations that achieve the same results as the identified object code operations; and

performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code comprises replacing, during translation, the identified object code operations with the alternative operations.

41. The system on chip of claim 37, wherein:

the one or more cores are configured with processor-executable instructions so the system on chip performs operations further comprising sensing a connection to a new power source; and

the one or more cores are configured with processor-executable instructions so the system on chip performs operations such that performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code is performed when connection to the new power source is sensed.

42. The system on chip of claim 37, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations such that analyzing the received object code comprises using a power consumption model to identify segments of object code that can be optimized for power efficiency.

43. The system on chip of claim 42, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations comprising:

measuring an amount of power consumed in the execution of segments of power optimized object code;

comparing the measured amount of power consumed to predictions of the power consumption model; and

modifying the power consumption model based on a result of the comparison.