Dynamic Power Optimization For Computing Devices
First Claim
1. A method for optimizing object code for power savings during execution on a computing device, comprising:
- receiving compiled binary object code in a computing device'"'"'s system software;
analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;
performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and
executing the power optimized object code on a processor of the computing device.
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Accused Products
Abstract
In the various aspects, virtualization techniques may be used to reduce the amount of power consumed by execution of applications by power-optimizing the code prior to execution. A dynamic binary translator operating at the machine layer may use a power consumption model to identify code segments that can benefit from optimization and to perform an instruction-sequence to instruction-sequence translation of object code to generate power-optimized object code. Execution hardware may be instrumented with additional circuitry to measure the power consumption characteristics of executing code. The power consumption models may be updated and object code may be regenerated based on the measured the power consumption characteristics of previously executed code. In an aspect, power optimization may be accomplished when the computing device is connected to a battery charger.
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Citations
43 Claims
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1. A method for optimizing object code for power savings during execution on a computing device, comprising:
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receiving compiled binary object code in a computing device'"'"'s system software; analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings; performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and executing the power optimized object code on a processor of the computing device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computing device configured to optimize object code during execution for improved power savings, comprising:
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means for receiving compiled binary object code in system software; means for analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings; means for performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and means for executing the power optimized object code on a processor of the computing device. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A computing device, comprising:
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a memory; and one or more processors coupled to the memory, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations comprising; receiving compiled binary object code in system software; analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings; performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and executing the power optimized object code. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations for optimizing object code for power savings during execution on a computing device, the operations comprising:
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receiving compiled binary object code in system software; analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings; performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and executing the power optimized object code on a processor of the computing device. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36)
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37. A system on chip, comprising:
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a memory; and one or more cores coupled to the memory, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations comprising; receiving in an operating system compiled binary object code; analyzing the received object code in a dynamic binary translator process operating at the machine layer to identify code segments that can be optimized for power savings; performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code; and executing the power optimized object code. - View Dependent Claims (38, 39, 40, 41, 42, 43)
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Specification