NON-VOLATILE MEMORY DEVICE

• US 20130075684A1
• Filed: 08/17/2012
• Published: 03/28/2013
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kinoshita, Masaharu, Sasago, Yoshitaka, Kobayashi, Takashi, Minemura, Hiroyuki
• Granted Patent: US 8,642,988 B2
• Time in Patent Office: Days
• US Class Current: 257/2
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.

Claims

1. A non-volatile memory device comprising:

a substrate;

a first line extending in a first direction, the first direction being parallel to a main surface of the substrate;

a stack comprising N+1 layers (where N≧

1) of first insulator films and N layers of first semiconductor layers, the first insulator films and the first semiconductor layers being alternately stacked above the first line;

a second line formed above the stack and extending in a second direction, the second direction being parallel to the main surface of the substrate and orthogonal to the first direction;

a select element provided at a point where the first line and the second line intersect;

a second insulator film provided along a side surface of the stack;

a channel layer provided along the second insulator film;

an adhesion layer provided along the channel layer; and

a variable resistance material layer provided along the channel layer with the adhesion layer in-between, wherein

the first line and the second line are electrically connected with each other via the select element and the channel layer, and

a contact resistance via the adhesion layer between the channel layer and the variable resistance material layer is low, and a resistance of the adhesion layer in a direction in which the channel layer extends is high.

2. The non-volatile memory device according to claim 1, wherein the adhesion layer comprises a film that is discontinuous with respect to the direction in which the channel layer extends.

3. The non-volatile memory device according to claim 1, wherein the adhesion layer comprises a metal comprising Ti, Cr, Co, Ni, or W, or a compound thereof.

4. The non-volatile memory device according to claim 1, wherein the adhesion layer comprises a silicon dot.

5. The non-volatile memory device according to claim 4, wherein the silicon dot is doped with an impurity.

6. The non-volatile memory device according to claim 1, wherein the adhesion layer is provided only at a height range of the first insulator film with respect to the direction in which the channel layer extends.

7. A non-volatile memory device comprising:

a substrate;

a first line extending in a first direction, the first direction being parallel to a main surface of the substrate;

a stack comprising N+1 layers (where N≧

1) of first insulator films and N layers of first semiconductor layers, the first insulator films and the first semiconductor layers being alternately stacked above the first line, side surfaces of the first insulator films, which form a portion of a side surface of the stack, being formed so as to be one step recessed relative to side surfaces of the first semiconductor layers;

a second line formed above the stack and extending in a second direction, the second direction being parallel to the main surface of the substrate and orthogonal to the first direction;

a select element provided at a point where the first line and the second line intersect;

a second insulator film provided along the side surface of the stack;

a channel layer provided along the second insulator film;

an adhesion layer provided only at the same height ranges as the side surfaces of the first insulator films with respect to a direction in which the channel layer extends; and

a variable resistance material layer provided along side surfaces of the channel layer and the adhesion layer, wherein

the first line and the second line are electrically connected with each other via the select element and the channel layer, and

a contact resistance via the adhesion layer between the channel layer and the variable resistance material layer is low, and a resistance of the adhesion layer in the direction in which the channel layer extends is high.

8. The non-volatile memory device according to claim 7, further comprising third insulator films respectively provided on both an upper surface side and a lower surface side of the stack, wherein

an etching rate of the third insulator films is lower than an etching rate of the first insulator films.

9. The non-volatile memory device according to claim 8, wherein

the first insulator films comprise silicon oxide, and

the third insulator films comprise silicon nitride or silicon oxynitride.

10. The non-volatile memory device according to claim 7, wherein a fourth insulator film is provided between the channel layer and the variable resistance material layer excluding the ranges where the adhesion layer is provided.

11. The non-volatile memory device according to claim 7, wherein the adhesion layer comprises a metal comprising Ti, Cr, Co, Ni, or W, or a compound thereof.

12. The non-volatile memory device according to claim 7, wherein the adhesion layer comprises a silicon dot.

13. The non-volatile memory device according to claim 12, wherein the silicon dot is doped with an impurity.