Lateral PNP Bipolar Transistor with Narrow Trench Emitter

• US 20130075746A1
• Filed: 09/23/2011
• Published: 03/28/2013
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Mallikarjunaswamy, Shekar, Hbert, Franois
• Granted Patent: US 9,312,335 B2
• Time in Patent Office: Days
• US Class Current: 257/75
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0808 of lateral transistors
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/735 Lateral transistors

Abstract

A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.

Claims

1. A lateral bipolar transistor, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of a second conductivity type formed on the substrate, the second conductivity type being opposite the first conductivity type;

a first buried layer of the first conductivity type and a second buried layer of the second conductivity type both formed between the substrate and the epitaxial layer, the first buried layer being located under a trench isolation structure and the second buried layer being located under a base region;

a dielectric layer formed over the epitaxial layer;

first and second trenches formed in the dielectric layer and the epitaxial layer, the trenches being filled with at least one polysilicon layer, the polysilicon layer being insulated from at least a bottom portion of each trench by a dielectric layer, and the polysilicon layer being doped with dopants of the first conductivity type; and

first and second diffusion regions of the first conductivity type formed in the epitaxial layer surrounding sidewalls of respective first and second trenches, the polysilicon layer of each trench being in electrical contact with the respective diffusion region surrounding sidewalls of the respective trench,

wherein an emitter region is formed in the first trench and the first diffusion region, a collector region is formed in the second trench and the second diffusion region, the base region being formed in the epitaxial layer between the first and second diffusion regions associated with the first and second trenches, the polysilicon layer in the first trench being formed over the dielectric layer and extending over a portion of the base region, the extended portion of the polysilicon layer of the first trench functioning as a field plate for the base region.

2. The lateral bipolar transistor of claim 1, wherein the first and second trenches are filled with a first polysilicon layer at a lower portion of each trench and a second polysilicon layer at an upper portion of each trench, the first polysilicon layer being insulated from the sidewalls and the bottom portions of the trenches by a thin oxide layer, and the second polysilicon layer being heavily doped with dopants of the first conductivity type.

3. The lateral bipolar transistor of claim 2, wherein the dielectric layer formed over the epitaxial layer comprises an oxide hardmask.

4. The lateral bipolar transistor of claim 2, wherein the dielectric layer formed over the epitaxial layer comprises a nitride layer.

5. The lateral bipolar transistor of claim 1, wherein the first and second trenches are each filled with an oxide layer formed at a bottom portion of each trench and the remainder of the trenches is further filled with a polysilicon layer being heavily doped with dopants of the first conductivity type, the first and second diffusion regions being formed by out-diffusion of dopants from the heavily doped polysilicon layer.

6. The lateral bipolar transistor of claim 5, wherein the dielectric layer formed over the epitaxial layer comprises an oxide layer.

7. The lateral bipolar transistor of claim 5, wherein the dielectric layer formed over the epitaxial layer comprises an oxide layer overlying a nitride layer.

8. The lateral bipolar transistor of claim 1, further comprising:

first and second trench bottom diffusion regions of the second conductivity type, each trench bottom diffusion region being formed beneath a bottom of the respective first or second trench.

9. The lateral bipolar transistor of claim 1, further comprising:

an emitter contact contacting the polysilicon layer formed in the first trench; and

a collector contact contacting the polysilicon layer formed in the second trench.

10. The lateral bipolar transistor of claim 1, further comprising:

a sinker diffusion region of the second conductivity type formed in the epitaxial layer and extending to and being in electrical contact with the second buried layer.

11. The lateral bipolar transistor of claim 10, further comprising:

a base contact contacting the sinker diffusion region.

12. The lateral bipolar transistor of claim 1, further comprising:

a third trench formed in the dielectric layer and the epitaxial layer, the third trench being filled with the at least one polysilicon layer, the polysilicon layer being insulated from at least a bottom portion of the third trench by a dielectric layer; and

the polysilicon layer being doped with dopants of the first conductivity type; and

a third diffusion region of the first conductivity type formed surrounding sidewalls of the third trench, the polysilicon layer of the third trench being in electrical contact with the third diffusion region surrounding sidewalls of the third trench,

wherein the trench isolation structure is formed in the third trench, the third trench having a width wider than the first and second trenches and having a depth deeper than the first and second trenches, the third diffusion region extending to and being in electrical contact with the first buried layer.

13. The lateral bipolar transistor of claim 1, further comprising:

a fourth diffusion region of the second conductivity type formed surrounding the first diffusion region of the first trench; and

a fifth diffusion region of the second conductivity type formed surrounding the second diffusion region of the second trench,

wherein the fourth and fifth diffusion regions each has a dopant level higher than the dopant level of the epitaxial layer.

14. The lateral bipolar transistor of claim 13, wherein the fourth diffusion region associated with the first trench and the fifth diffusion region associated with the second trench are separated by a lateral distance in the epitaxial layer.

15. The lateral bipolar transistor of claim 13, wherein the fourth diffusion region associated with the first trench abuts the fifth diffusion region associated with the second trench.

16. The lateral bipolar transistor of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

17. A method for fabricating a lateral bipolar transistor, comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first buried layer of the first conductivity type and a second buried layer of a second conductivity type in the substrate, the second conductivity type being opposite the first conductivity type, the first buried layer being located under a trench isolation structure and the second buried layer being located under a base region;

forming an epitaxial layer of the second conductivity type on the substrate;

forming a dielectric layer over the epitaxial layer;

forming first and second trenches in the dielectric layer and the epitaxial layer;

forming first and second diffusion regions of the first conductivity type in the epitaxial layer surrounding sidewalls of respective first and second trenches;

forming a lining oxide layer and a first polysilicon layer in a lower portion of each trench, the first polysilicon layer being insulated from the sidewalls of the trenches by the lining oxide layer;

forming a second polysilicon layer at an upper portion of each trench, the second polysilicon layer being heavily doped with the first conductivity type and the second polysilicon layer of each trench being in electrical contact with the respective diffusion region surrounding sidewalls of the respective trench; and

forming an extended portion of the second polysilicon layer of the first trench over the dielectric layer and extending over a portion of the base region, the extended portion of the second polysilicon layer of the first trench functioning as a field plate for the base region,

wherein an emitter region is formed in the first trench and the first diffusion region, a collector region is formed in the second trench and the second diffusion region, the base region being formed in the epitaxial layer between the first and second diffusion regions associated with the first and second trenches.

18. The method of claim 17, further comprising:

forming first and second trench bottom diffusion regions of the second conductivity type, each trench bottom diffusion region being formed beneath a bottom of the respective first or second trench.

19. The method of claim 17, further comprising:

forming a sinker diffusion region of the second conductivity type in the epitaxial layer and extending to and being in electrical contact with the second buried layer.

20. The method of claim 17, further comprising:

forming a third trench in the dielectric layer and the epitaxial layer;

forming a third diffusion region of the first conductivity type in the epitaxial layer surrounding sidewalls of the third trench;

forming a lining oxide layer and a first polysilicon layer in a lower portion of the third trench, the first polysilicon layer being insulated from the sidewalls of the third trench by the lining oxide layer; and

forming a second polysilicon layer at an upper portion of the third trench, the second polysilicon layer being heavily doped with the first conductivity type and the second polysilicon layer of the third trench being in electrical contact with the respective diffusion region surrounding sidewalls of the third trench,

wherein the trench isolation structure is formed in the third trench, the third trench having a width wider than the first and second trenches and having a depth deeper than the first and second trenches, the third diffusion region extending to and being in electrical contact with the first buried layer.

21. The method of claim 17, further comprising:

forming a fourth diffusion regions of the second conductivity type surrounding the first diffusion region of the first trench; and

forming a fifth diffusion regions of the second conductivity type surrounding the second diffusion region of the second trench,

wherein the fourth and fifth diffusion regions each has a dopant level higher than the dopant level of the epitaxial layer.

22. The method of claim 21, wherein the fourth diffusion region associated with the first trench and the fifth diffusion region associated with the second trench are separated by a lateral distance in the epitaxial layer.

23. The method of claim 21, wherein the fourth diffusion region associated with the first trench abuts the fifth diffusion region associated with the second trench.

24. The method of claim 17, wherein the first conductivity type is P-type and the second conductivity type is N-type.

25. The method of claim 17, wherein forming a dielectric layer over the epitaxial layer comprises forming an oxide hardmask over the epitaxial layer.

26. The method of claim 17, wherein forming a dielectric layer over the epitaxial layer comprises forming a nitride layer over the epitaxial layer and forming an oxide hardmask over the nitride layer, the method further comprising:

removing the oxide hardmask before forming a lining oxide layer and a first polysilicon layer.

27. The method of claim 17, wherein forming first and second diffusion regions of the first conductivity type in the epitaxial layer surrounding sidewalls of respective first and second trenches comprises:

implanting dopants of the first conductivity type into the first and second trenches, the implanting being performing using multiple title angles with rotation.

28. A method for fabricating a lateral bipolar transistor, comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first buried layer of the first conductivity type and a second buried layer of a second conductivity type in the substrate, the second conductivity type being opposite the first conductivity type, the first buried layer being located under a trench isolation structure and the second buried layer being located under a base region;

forming an epitaxial layer of the second conductivity type on the substrate;

forming a dielectric masking layer over the epitaxial layer;

forming first and second trenches in the dielectric masking layer and the epitaxial layer;

removing the dielectric masking layer;

forming a second dielectric layer over the epitaxial layer and in the first and second trenches;

isotropically etching the second dielectric layer to leave the second dielectric layer on a top surface of the epitaxial layer and on a bottom portion of each trench;

forming a polysilicon layer over the second dielectric layer and in each trench, the polysilicon layer being heavily doped with the first conductivity type;

patterning the polysilicon layer to form polysilicon regions associated with each trench and to form an extended portion of the polysilicon layer of the first trench over the second dielectric layer and extending over a portion of the base region, the extended portion of the polysilicon layer of the first trench functioning as a field plate for the base region; and

annealing the epitaxial layer and the polysilicon layer to form by dopant out-diffusion first and second diffusion regions of the first conductivity type in the epitaxial layer surrounding sidewalls of respective first and second trenches, the polysilicon layer of each trench being in electrical contact with the respective diffusion region surrounding sidewalls of the respective trench,

wherein an emitter region is formed in the first trench and the first diffusion region, a collector region is formed in the second trench and the second diffusion region, the base region being formed in the epitaxial layer between the first and second diffusion regions associated with the first and second trenches.

29. The method of claim 28, further comprising:

forming a sinker diffusion region of the second conductivity type in the epitaxial layer and extending to and being in electrical contact with the second buried layer.

30. The method of claim 28, further comprising:

forming a third trench in the insulating layer and the epitaxial layer;

forming the second dielectric layer in a bottom portion of the third trench;

forming the polysilicon layer in the third trench; and

annealing the epitaxial layer and the polysilicon layer to form by dopant out-diffusion a third diffusion region of the first conductivity type in the epitaxial layer surrounding sidewalls of the third trench, the polysilicon layer of the third trench being in electrical contact with the third diffusion region surrounding sidewalls of the third trench,

wherein the trench isolation structure is formed in the third trench, the third trench having a width wider than the first and second trenches and having a depth deeper than the first and second trenches, the third diffusion region extending to and being in electrical contact with the first buried layer.

31. The method of claim 28, further comprising:

forming a fourth diffusion regions of the second conductivity type surrounding the first diffusion region of the first trench; and

forming a fifth diffusion regions of the second conductivity type surrounding the second diffusion region of the second trench,

wherein the fourth and fifth diffusion regions each has a dopant level higher than the dopant level of the epitaxial layer.

32. The method of claim 31, wherein the fourth diffusion region associated with the first trench and the fifth diffusion region associated with the second trench are separated by a lateral distance in the epitaxial layer.

33. The method of claim 31, wherein the fourth diffusion region associated with the first trench abuts the fifth diffusion region associated with the second trench.

34. The method of claim 28, wherein the first conductivity type is P-type and the second conductivity type is N-type.

35. The method of claim 28, wherein forming a dielectric masking layer over the epitaxial layer comprises forming an oxide hardmask over the epitaxial layer.

36. The method of claim 28, wherein forming a dielectric masking layer over the epitaxial layer comprises forming a nitride layer over the epitaxial layer and forming an oxide hardmask over the nitride layer.