SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20130075797A1
• Filed: 08/30/2012
• Published: 03/28/2013
• Est. Priority Date: 09/22/2011
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OKANO, Kimitoshi
• Application Number:
  US13/599,025
• Publication Number:
  US 20130075797A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate, and a fin disposed on a surface of the semiconductor substrate and having a side surface of a (110) plane. The device further includes a gate insulator disposed on the side surface of the fin, and a gate electrode disposed on the side surface and an upper surface of the fin via the gate insulator. The device further includes a plurality of epitaxial layers disposed on the side surface of the fin in order along a height direction of the fin.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a fin disposed on a surface of the semiconductor substrate, and having a side surface of a (110) plane;

a gate insulator disposed on the side surface of the fin;

a gate electrode disposed on the side surface and an upper surface of the fin via the gate insulator; and

a plurality of epitaxial layers disposed on the side surface of the fin in order along a height direction of the fin.

2. The device of claim 1, wherein the epitaxial layers have facet surfaces of (111) planes.

3. The device of claim 1, further comprising silicide layers disposed in the epitaxial layers.

4. The device of claim 1, wherein

the fin includes one or more first semiconductor layers and one or more second semiconductor layers alternately stacked on the semiconductor substrate, and

the epitaxial layers are disposed on side surfaces of respective second semiconductor layers.

5. The device of claim 4, wherein the epitaxial layers are further disposed on side surfaces of respective first semiconductor layers.

6. The device of claim 4, wherein thicknesses of the first semiconductor layers are smaller than thicknesses of the second semiconductor layers.

7. The device of claim 4, wherein side surfaces of the first semiconductor layers are recessed with respect to the side surfaces of the second semiconductor layers in the fin.

8. The device of claim 7, wherein an insulator is embedded in a region where the side surfaces of the first semiconductor layers are recessed in the fin.

9. The device of claim 1, wherein

the fin includes one or more insulators and one or more semiconductor layers alternately stacked on the semiconductor substrate, and

the epitaxial layers are disposed on side surfaces of respective semiconductor layers.

10. The device of claim 1, further comprising a pad portion disposed at a tip portion of the fin,

wherein the pad portion includes the one or more insulators, the one or more semiconductor layers, and one or more connection semiconductor layers disposed in the insulators to connect the semiconductor layers with each other.

11. A method of manufacturing a semiconductor device, the method comprising:

forming a fin having a side surface of a (110) plane on a surface of a semiconductor substrate;

forming a gate electrode on a side surface and an upper surface of the fin via a gate insulator formed on the side surface of the fin;

covering the fin with an insulator; and

forming a plurality of epitaxial layers on the side surface of the fin in order along a height direction of the fin, by alternately repeating processing of reducing a height of an upper surface of the insulator and processing of forming an epitaxial layer on the side surface of the fin.

12. The method of claim 11, wherein the epitaxial layers are formed to have facet surfaces of (111) planes.

13. The method of claim 11, further comprising forming silicide layers in the epitaxial layers.

14. The method of claim 11, wherein

the fin is formed to include one or more first semiconductor layers and one or more second semiconductor layers alternately stacked on the semiconductor substrate, and

the epitaxial layers are formed on side surfaces of respective second semiconductor layers.

15. The method of claim 14, wherein the epitaxial layers are further formed on side surfaces of respective first semiconductor layers.

16. The method of claim 14, wherein thicknesses of the first semiconductor layers are set smaller than thicknesses of the second semiconductor layers.

17. The method of claim 14, further comprising recessing side surfaces of the first semiconductor layers with respect to the side surfaces of the second semiconductor layers in the fin.

18. The method of claim 17, further comprising embedding an insulator in a region where the side surfaces of the first semiconductor layers are recessed in the fin.

19. The method of claim 11, wherein

the fin is formed to include one or more insulators and one or more semiconductor layers alternately stacked on the semiconductor substrate, and

the epitaxial layers are formed on side surfaces of respective semiconductor layers.

20. The method of claim 11, further comprising forming a pad portion at a tip portion of the fin,

wherein the pad portion is formed to include the one or more insulators, the one or more semiconductor layers, and one or more connection semiconductor layers formed in the insulators to connect the semiconductor layers with each other.