SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR VIA

• US 20130075814A1
• Filed: 09/23/2011
• Published: 03/28/2013
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meiser, Andreas Peter, Zundel, Markus
• Granted Patent: US 10,032,878 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor body having a first surface and a second surface, at least one electrode arranged in at least one trench extending from the first surface into the semiconductor body, and a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface. The semiconductor via is electrically insulated from the semiconductor body by a via insulation layer. The at least one electrode extends in a first lateral direction of the semiconductor body through the via insulation layer and is electrically connected to the semiconductor via.

Claims

1. A semiconductor device, comprising:

a semiconductor body having a first surface and a second surface;

at least one electrode arranged in at least one trench extending from the first surface into the semiconductor body;

a semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface, the semiconductor via being electrically insulated from the semiconductor body by a via insulation layer; and

wherein the at least one electrode extends in a first lateral direction of the semiconductor body through the via insulation layer and is electrically connected to the semiconductor via.

2. The semiconductor device of claim 1, wherein the semiconductor device is a transistor device in which the at least one electrode forms a gate electrode.

3. The semiconductor device of claim 2, further comprising:

a source region, a body region, a drift region and a drain region, the body region being arranged between the source region and the drift region and the drift region being arranged between the body region and the drain region;

a source electrode arranged on the first surface and electrically connected to the source region;

a drain electrode arranged on the second surface and electrically connected to the drain region; and

a gate dielectric dielectrically insulating the gate electrode from the source region and the body region.

4. The semiconductor device of claim 3, wherein the drift region and the drain region have the same doping type.

5. The semiconductor device of claim 3, wherein the drift region and the drain region have complementary doping types.

6. The semiconductor device of claim 1, further comprising:

a field electrode arranged in the at least one trench below the gate electrode with respect to the first surface and dielectrically insulated from the gate electrode; and

a field electrode dielectric dielectrically insulating the field electrode from the semiconductor body.

7. The semiconductor device of claim 6, wherein the field electrode in the first lateral direction is arranged distant to the via insulation layer.

8. The semiconductor device of claim 6, wherein the field electrode in the first lateral direction extends through the via insulation layer and is electrically insulated from the semiconductor via.

9. The semiconductor device of claim 1, wherein the semiconductor via further comprises a contact region electrically contacted by the gate electrode, the contact region having a higher doping concentration than regions of the semiconductor via adjoining the contact region.

10. The semiconductor device of claim 3, further comprising a plurality of transistor cells, each cell comprising a source zone, a body zone and a gate electrode.

11. The semiconductor device of claim 10, wherein the semiconductor via in a horizontal plane of the semiconductor body has a ring-shaped form and surrounds the plurality of transistor cells.

12. The semiconductor device according to claim 1, wherein the at least one electrode is electrically connected to a sensor integrated in the semiconductor body in a region of the first surface.

13. The semiconductor device of claim 12, wherein the sensor is one of a temperature sensor or a current sensor.

14. The semiconductor device of claim 1, further comprising at least two electrodes and at least two semiconductor vias, each of the electrodes being connected to one of the semiconductor vias.

15. A method for producing a semiconductor device, comprising:

providing a semiconductor body having a first surface, a second surface and a semiconductor via, the semiconductor via extending in a vertical direction of the semiconductor body within the semiconductor body to the second surface and being insulated from the semiconductor body by a via insulation layer;

etching at least one trench that extends from the first surface into the semiconductor body, wherein the at least one trench in a first lateral direction of the semiconductor body extends through the via insulation layer into the semiconductor via;

forming at least one electrode in the at least one trench such that the at least one electrode is dielectrically insulated from semiconductor regions of the semiconductor body and is electrically connected to the semiconductor via; and

forming a contact electrode on the semiconductor via on the second surface.

16. The method of claim 15, wherein the semiconductor device is a transistor device and the at least one electrode is a gate electrode.

17. The method of claim 16, wherein forming the at least one gate electrode further cornprises:

forming a gate dielectric at least on sidewalls of the at least one trench;

removing the gate dielectric from at least some surface regions of the at least one trench that adjoin the semiconductor via, so as to uncover the semiconductor via in the at least one trench; and

forming the gate electrode in the at least one trench on the gate dielectric and on uncovered regions of the semiconductor via.

18. The method of claim 15, further comprising prior to forming the gate electrode:

forming a field electrode in the at least one trench such that the field electrode is dielectrically insulated from the semiconductor body by a field electrode dielectric; and

forming an insulation layer on the field electrode in the at least one trench.

19. The method of claim 18, wherein forming the field electrode further comprises:

depositing a field electrode material in the at least one trench on the field electrode dielectric; and

removing the field electrode material from a first trench region in which the at least one trench adjoins the semiconductor via, while at least partially leaving the field electrode material in a second trench region distant to the semiconductor via, so as to form the field electrode.

20. The method of claim 19, wherein the at least one trench is formed such that a width of the at least one trench is larger in the first trench region than in the second trench region.

21. The method of claim 20, wherein forming the field electrode further comprises completely filling the at least one trench in the second trench region with the field electrode material, while only covering a bottom and sidewalls of the at least one trench in the first trench region.

22. The method of claim 21, further comprising etching back the field electrode material in the second trench region so as to form the field electrode, while removing the field electrode material in the first trench region.

23. The method of claim 15, wherein forming the at least one trench comprises:

removing the via insulation layer in a region adjoining the first surface, so as to form a ring-shaped trench surrounding the semiconductor via;

forming an etch mask that leaves sections of the semiconductor via and of the semiconductor via uncovered; and

etching the at least one trench in those regions of the semiconductor via that are not covered by the etch mask.

24. The method of claim 23, wherein forming the etch mask includes at least partially filling those regions of the ring-shaped trench covered by the etch mask.

25. The method of claim 24, wherein the etch mask remains in the ring-shaped trench and partially forms the via insulation layer.

26. The method of claim 15, wherein the semiconductor body has a first basic doping concentration in a region adjoining the first surface and regions of the semiconductor body having the basic doping concentration form a drift region, the method further comprising:

forming a source region and a body region, in a region of the first surface such that the body region is arranged between the source region and the drift region; and

forming a source electrode on the first surface.

27. The method of claim 26, wherein the semiconductor body has a second basic doping concentration in a region adjoining the second surface and the region having the second basic doping concentration forms a drain region, the method further comprising:

forming a drain electrode electrically contacting the drain region on the second surface.

28. The method of claim 25, further comprising:

forming a drain region in a region of the semiconductor body adjoining the second surface; and

forming a drain electrode electrically contacting the drain region on the second surface.