INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SUBSTRATE EMBEDDED DUMMY-DIE PADDLE AND METHOD OF MANUFACTURE THEREOF

• US 20130075922A1
• Filed: 09/23/2011
• Published: 03/28/2013
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Hin Hwa Goh, Kang Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
• Inventors: Huang, Rui, Bao, Xusheng, Chen, Kang, Hsiao, Yung Kuan, Goh, Hin Hwa
• Granted Patent: US 9,236,278 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/814 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/83104 by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down;

forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and

mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.

2. The method as claimed in claim 1 wherein providing the dummy-die paddle includes providing a through-silicon-via substrate having a through silicon via traversing the height of the dummy-die paddle.

3. The method as claimed in claim 1 wherein forming the insulator includes forming the insulator exposing the second inactive side from the insulator.

4. The method as claimed in claim 1 further comprising filling an under-fill between the integrated circuit and the dummy-die paddle.

5. The method as claimed in claim 1 further comprising forming a substrate in direct contact with the second inactive side.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a temporary carrier;

mounting a dummy-die paddle on the temporary carrier having;

a first inactive side facing up,

a second inactive side facing down, and

outer sides terminating at the first inactive side and the second inactive side;

mounting a lead frame with a pillar peripheral to the dummy-die paddle, and having;

a top side on a top, and

an exterior side terminating at the top side;

forming an insulator having a top surface around the dummy-die paddle and in direct contact with the first inactive side and the outer sides and molded around the pillars in direct contact with the top side and in a single continuous structure;

mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle; and

removing the temporary carrier.

7. The method as claimed in claim 6 further comprising forming vias through the insulator from the top surface of the insulator to the top side of the pillar.

8. The method as claimed in claim 6 wherein forming the insulator includes forming the insulator exposing the exterior side from the insulator.

9. The method as claimed in claim 6 further comprising:

forming a post over the dummy-die paddle;

forming a solder cap above the post; and

wherein;

mounting the integrated circuit includes electrically connecting the integrated circuit to the solder cap and the post.

10. The method as claimed in claim 6 further comprising forming a redistribution layer on the top surface of the insulator.

11. An integrated circuit packaging system comprising:

a dummy-die paddle having a first inactive side facing up, a second inactive side facing down;

an insulator in a single continuous structure around and in direct contact with the first inactive side; and

an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.

12. The system as claimed in claim 11 wherein the dummy-die paddle is a through-silicon-via substrate having a through silicon via traversing the height of the dummy-die paddle.

13. The system as claimed in claim 11 wherein the second inactive side is exposed from the insulator.

14. The system as claimed in claim 11 further comprising an under-fill filled between the integrated circuit and the dummy-die paddle.

15. The system as claimed in claim 11 further comprising a substrate in direct contact with the second inactive side.

16. The system as claimed in claim 11 further comprising a pillar mounted peripheral to the dummy-die paddle, and each pillar including:

a top side on a top; and

an exterior side terminating at the top side.

17. The system as claimed in claim 16 further comprising through the insulator from the top surface of the insulator to the top side of the pillar.

18. The system as claimed in claim 16 wherein the exterior side is exposed from the insulator.

19. The system as claimed in claim 16 further comprising:

a post over the dummy-die paddle;

a solder cap above the post; and

wherein;

the integrated circuit is electrically connected to the solder cap and the post.

20. The system as claimed in claim 16 further comprising a redistribution layer on the top surface of the insulator.