Semiconductor Device and Method of Forming Interconnect Substration for FO-WLCSP

• US 20130075936A1
• Filed: 09/23/2011
• Published: 03/28/2013
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Lin, Yaojian, Fang, Jianmin, Feng, Xia, Cheng, Kang
• Granted Patent: US 9,679,863 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68304 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68331 of passive members, e.g. die mounting substrate
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 Electroless plating
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2101 : Structure
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/215 : Material
• CPC Class Codes: H01L 2224/24155 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/245 : Material
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82106 : by subtractive methods
• CPC Class Codes: H01L 2224/82986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a first encapsulant deposited over a first carrier. A plurality of conductive vias is formed through the first encapsulant to provide an interconnect substrate. A first semiconductor die is mounted over a second carrier. The interconnect substrate is mounted over the second carrier adjacent to the first semiconductor die. A second semiconductor die is mounted over the second carrier adjacent to the interconnect substrate. A second encapsulant is deposited over the first and second semiconductor die, interconnect substrate, and second carrier. A first interconnect structure is formed over a first surface of the second encapsulant and electrically connected to the conductive vias. A second interconnect structure is formed over a second surface of the second encapsulant and electrically connected to the conductive vias to make the Fo-WLCSP stackable. Additional semiconductor die can be mounted over the first and second semiconductor die in a PoP arrangement.

Claims

1. A method of making a semiconductor device, comprising:

providing a first carrier;

depositing a first encapsulant over the first carrier;

forming a plurality of conductive vias through the first encapsulant to form an interconnect substrate;

providing a second carrier;

mounting first and second semiconductor die over the second carrier;

mounting the interconnect substrate over the second carrier adjacent to the first and second semiconductor die;

depositing a second encapsulant over the first and second semiconductor die, interconnect substrate, and second carrier;

forming a first interconnect structure over a first surface of the second encapsulant and electrically connected to the conductive vias of the interconnect substrate;

removing the second carrier; and

forming a second interconnect structure over a second surface of the second encapsulant opposite the first surface of the second encapsulant and electrically connected to the conductive vias of the interconnect substrate.

2. The method of claim 1, wherein forming the plurality of conductive vias includes:

forming a plurality of vias through the first encapsulant; and

depositing a conductive layer within the vias.

3. The method of claim 1, wherein a coefficient of thermal expansion of the interconnect substrate is similar to a coefficient of thermal expansion of the second encapsulant.

4. The method of claim 1, further including removing a portion of the second encapsulant to planarize the second encapsulant.

5. The method of claim 1, further including:

mounting a third semiconductor die over the first semiconductor die; and

mounting a fourth semiconductor die over the second semiconductor die.

6. The method of claim 1, wherein the interconnect structure is disposed around the first and second semiconductor die.

7. A method of making a semiconductor device, comprising:

forming an interconnect substrate having a plurality of conductive structures extending through the interconnect substrate;

providing a first carrier;

mounting the interconnect substrate over the first carrier;

mounting a plurality of first semiconductor die over the first carrier adjacent to the interconnect substrate;

depositing a first encapsulant over the first semiconductor die, interconnect substrate, and first carrier; and

forming a first interconnect structure over a first surface of the first encapsulant and electrically connected to the conductive structures of the interconnect substrate.

8. The method of claim 7, further including forming a second interconnect structure over a second surface of the first encapsulant opposite the first surface of the first encapsulant and electrically connected to the conductive structures of the interconnect substrate.

9. The method of claim 8, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first and second interconnect structures and interconnect substrate.

10. The method of claim 7, wherein forming the interconnect substrate includes:

providing a second carrier;

depositing a second encapsulant over the second carrier;

forming a plurality of vias through the second encapsulant; and

forming a conductive layer within the vias.

11. The method of claim 7, wherein the interconnect structures through the interconnect substrate include bumps, conductive vias, or conductive pillars.

12. The method of claim 11, wherein the bumps include rounded bumps and polygon shaped bumps.

13. The method of claim 7, further including:

mounting a second semiconductor die over one of the first semiconductor die; and

mounting a third semiconductor die over another one of the first semiconductor die.

14. A method of making a semiconductor device, comprising:

forming an interconnect substrate having a plurality of conductive structures;

disposing a first semiconductor die adjacent to the interconnect structure;

depositing a first encapsulant over the first semiconductor die and interconnect substrate; and

forming a first interconnect structure over a first surface of the first encapsulant and electrically connected to the conductive structures of the interconnect substrate.

15. The method of claim 14, further including forming a second interconnect structure over a second surface of the first encapsulant opposite the first surface of the first encapsulant and electrically connected to the conductive structures of the interconnect substrate.

16. The method of claim 15, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first and second interconnect structures and interconnect substrate.

17. The method of claim 14, wherein forming the interconnect substrate includes:

providing a carrier;

depositing a second encapsulant over the carrier;

forming a plurality of vias through the second encapsulant; and

forming a conductive layer within the vias.

18. The method of claim 14, wherein the interconnect structures through the interconnect substrate include bumps, conductive vias, or conductive pillars.

19. The method of claim 17, wherein the bumps include rounded bumps and polygon shaped bumps.

20. The method of claim 14, further including:

mounting a second semiconductor die over one of the first semiconductor die; and

mounting a third semiconductor die over another one of the first semiconductor die.

21. A semiconductor device, comprising:

an interconnect substrate having a plurality of conductive structures;

a first semiconductor die disposed adjacent to the interconnect structure;

an encapsulant deposited over the first semiconductor die and interconnect substrate; and

a first interconnect structure formed over a first surface of the encapsulant and electrically connected to the conductive structures of the interconnect substrate.

22. The semiconductor device of claim 21, further including a second interconnect structure formed over a second surface of the encapsulant opposite the first surface of the encapsulant and electrically connected to the conductive structures of the interconnect substrate.

23. The semiconductor device of claim 22, further including a plurality of stacked semiconductor devices electrically connected through the first and second interconnect structures and interconnect substrate.

24. The semiconductor device of claim 21, wherein the interconnect structures through the interconnect substrate include bumps, conductive vias, or conductive pillars.

25. The semiconductor device of claim 21, further including a second semiconductor die mounted over the first semiconductor die.