SEMICONDUCTOR DEVICE

• US 20130076395A1
• Filed: 12/21/2011
• Published: 03/28/2013
• Est. Priority Date: 09/27/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Mi-Hye Kim
• Inventors: KIM, Mi-Hye
• Granted Patent: US 8,581,620 B2
• Time in Patent Office: Days
• US Class Current: 326/87
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A semiconductor device includes a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code, a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code, and an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

Claims

1. A semiconductor device, comprising:

a code generator configured to generate a supplementary code with a value changing in response to a variation of an impedance code;

a main driver configured to receive an output data and drive the received output data to a data output pad, wherein a driving force of the main driver is controlled according to the impedance code; and

an auxiliary driver configured to receive the output data and drive the received output data to the data output pad, wherein a driving force of the auxiliary driver is controlled according to the supplementary code.

2. The semiconductor device of claim 1, wherein the impedance code has a value controlled according to a change in process, voltage and temperature (PVT).

3. The semiconductor device of claim 1, further comprising:

a driving control signal generator configured to generate a driving control signal enabled for a time period in response to a logic level change of the output data to control an operation of the auxiliary driver.

4. The semiconductor device of claim 1, wherein the auxiliary driver is enabled to drive the data output pad during an initial period after each change of the output data and is disabled after the initial period.

5. The semiconductor device of claim 1, wherein the code generator is configured to receive the impedance code and logically combine the impedance code to produce the supplementary code.

6. A semiconductor device, comprising:

a code generator configured to generate a pull-up supplementary code and a pull-down supplementary code, wherein the pull-up supplementary code and the pull-down supplementary code change in response to a variation of a pull-up impedance code and a variation of a pull-down impedance code, respectively;

a pull-up driver configured to receive an output data and pull-up drive a data output pad by using a plurality of main pull-up drivers and a plurality of auxiliary pull-up drivers; and

a pull-down driver configured to receive the output data and pull-down drive the data output pad by using a plurality of main pull-down drivers and a plurality of auxiliary pull-down drivers,

wherein the main pull-up drivers are controlled to be turned on/off in response to the pull-up impedance code and the auxiliary pull-up drivers are controlled to be turned on/off in response to the pull-up supplementary code, and

the main pull-down drivers are controlled to be turned on/off in response to the pull-down impedance code, and the auxiliary pull-down drivers are controlled to be turned on/off in response to the pull-down supplementary code.

7. The semiconductor device of claim 6, wherein the main pull-up drivers and the auxiliary pull-up drivers each comprise a PMOS transistor, and

the main pull-down drivers and the auxiliary pull-down drivers each comprise an NMOS transistor.

8. The semiconductor device of claim 6, wherein the pull-up impedance code and the pull-down impedance code have values varying in opposite to each other according to a change in process, voltage and temperature (PVT).

9. The semiconductor device of claim 8, wherein the pull-up impedance code has a value decreasing according to a decreasing level of an external power source voltage and has a value increasing according to an increasing level of the external power source voltage, and

the pull-down impedance code has a value increasing according to a decreasing level of the external power source voltage and has a value decreasing according to an increasing level of the external power source voltage.

10. The semiconductor device of claim 8, wherein the code generator comprises:

a pull-up supplementary code generation unit configured to vary a value of the pull-up supplementary code with a different variation range that is decided according to a variation of a value of the pull-up impedance code; and

a pull-down supplementary code generation unit configured to vary a value of the pull-down supplementary code with a different variation range that is decided according to a variation of a value of the pull-down impedance code.

11. The semiconductor device of claim 6, further comprising:

a pull-up driving control signal generator configured to generate a pull-up driving control signal which is enabled for a time period in response to a logic level of the output data transitioning from a logic high level to a logic low level and controls operations of the auxiliary pull-up drivers; and

a pull-down driving control signal generator configured to generate a pull-down driving control signal which is enabled for a time period in response to a logic level of the output data transitioning from a logic low level to a logic high level and controls operations of the auxiliary pull-down drivers.

12. The semiconductor device of claim 8, wherein the main pull-up drivers are first to third main pull-up drivers having operations respectively controlled in response to first to third bit values of the pull-up impedance code;

the auxiliary pull-up drivers are first and second auxiliary pull-up drivers having operations respectively controlled in response to first and second bit values of the pull-up supplementary code;

the main pull-down drivers are first to third main pull-down drivers having operations respectively controlled in response to first to third bit values of the pull-down impedance code; and

the auxiliary pull-down drivers are first and second auxiliary pull-down drivers having operations respectively controlled in response to first and second bit values of the pull-down supplementary code.

13. The semiconductor device of claim 12, wherein a driving strength of the first main pull-up driver has a greater value than a driving strength of the second main pull-up driver, and

a driving strength of the second main pull-up driver has a greater value than a driving strength of the third main pull-up driver, and

a driving strength of the second main pull-down driver has a greater value than a driving strength of the second main pull-down driver, and

a driving strength of the second main pull-down driver has a greater value than a driving strength of the third main pull-down driver.

14. The semiconductor device of claim 13, wherein a driving strength of the first auxiliary pull-up driver is greater than a driving strength of the second auxiliary pull-up driver, and

a driving strength of the first main pull-up driver is N times greater than a driving strength of the first auxiliary pull-up driver, wherein N is an integer greater than 2, and

a driving strength of the first auxiliary pull-down driver is greater than a driving strength of the second auxiliary pull-down driver, and

a driving strength of the first main pull-down driver is greater than a driving strength of the first auxiliary pull-down driver.

15. The semiconductor device of claim 12, wherein the first to third main pull-up drivers have the same driving strength, and

the first to third main pull-down drivers have the same driving strength.

16. The semiconductor device of claim 15, wherein the first and second auxiliary pull-up drivers have the same driving strength, where a driving strength of the first to third main pull-up drivers is N times greater than the driving strength of the first and second auxiliary pull-up drivers and N is an integer greater than 2, and

the first and second auxiliary pull-down drivers have the same driving strength, where a driving strength of the first to third main pull-down drivers is N times greater than the driving strength of the first and second auxiliary pull-down drivers and N is an integer greater than 2.

17. The semiconductor device of claim 12, wherein the code generator comprises:

a pull-up supplementary code generation unit configured to increase the number of bits that are enabled among the first and second bits of the pull-up supplementary code as the number of enabled bits among the first to third bits of the pull-up impedance code decreases; and

a pull-down supplementary code generation unit for increasing the number of bits that are enabled among the first and second bits of the pull-down supplementary code as the number of enabled bits among the first to third bits of the pull-down impedance code decreases.

18. The semiconductor device of claim 17, wherein the pull-up supplementary code generation unit comprises:

first and second inverters configured to respectively invert first and second bits of the pull-up impedance code;

a first NAND gate and a third inverter configured to perform an AND operation on an output signal of the first inverter and an output signal of the second inverter;

a fourth inverter configured to invert a third bit of the pull-up impedance code;

a first NOR gate configured to perform a NOR operation on an output signal of the third inverter and an output signal of a fourth inverter and output a second bit of the pull-up supplementary code; and

a second NOR gate and a fifth inverter configured to perform an OR operation on second and third bits of the pull-up impedance code and output a first bit of the pull-up supplementary code.

19. The semiconductor device of claim 18, wherein the pull-down supplementary code generation unit comprises:

sixth and seventh inverters configured to respectively invert first and second bits of the pull-down impedance code;

a second NAND gate and an eighth inverter configured to perform an AND operation on an output signal of the sixth inverter and an output signal of the seventh inverter;

a ninth inverter configured to invert a third bit of the pull-down impedance code;

a third NOR gate configured to perform a NOR operation on an output signal of the eighth inverter and an output signal of a ninth inverter and output a second bit of the pull-down supplementary code; and

a fourth NOR gate and a tenth inverter configured to perform an OR operation on second and third bits of the pull-down impedance code and output a first bit of the pull-down supplementary code.