High Performance Divider Using Feed Forward, Clock Amplification and Series Peaking Inductors

• US 20130076408A1
• Filed: 09/23/2011
• Published: 03/28/2013
• Est. Priority Date: 09/23/2011
• Status: Active Grant

• Current Assignee: Tensorcom Inc
• Original Assignee: Tensorcom Inc
• Inventors: Soe, Zaw
• Granted Patent: US 8,680,899 B2
• Time in Patent Office: Days
• US Class Current: 327/117
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider

Abstract

A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Claims

1. A switched differential amplifier comprising:

a first differential cell;

a load with a center tap coupling each leg of the first differential cell to a first power supply;

a plurality of switches coupling a source of the first differential cell to a second power supply;

each of the plurality of switches receiving a different signal, and

at least one of the different signals has a different phase than the remaining signals.

2. The apparatus of claim 1, further comprising:

a second differential cell;

each leg of the second differential transistor corresponds to an equivalent leg in the first differential cell;

each leg of the second differential cell is coupled to the corresponding center taps; and

a single switch coupling a source of the second differential cell to the second power supply.

3. The apparatus of claim 1, whereby

the load is a series coupling of a resistor and a series peaking inductor.

4. The apparatus of claim 3, further comprising:

a capacitance coupled to each leg of the first differential cell forming an RLC network.

5. The apparatus of claim 4, whereby

the capacitance value can be electrically adjusted.

6. The apparatus of claim 5, whereby

an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.

7. The apparatus of claim 2, further comprising:

a current mirror coupled to the single switch that adjusts a current flow through the single switch.

8. The apparatus of claim 7, whereby

the current flow adjusts a resonant characteristic of the RLC network.

9. A differential amplifier comprising:

a first differential cell;

a load with a center tap coupling each leg of the first differential cell to a first power supply;

a current control coupling the first differential cell to a second power supply;

a second differential cell;

each leg of the second differential transistor corresponds to an equivalent leg in the differential cell;

each leg of the second differential cell is coupled to the corresponding center taps; and

a single switch coupling a source of the second differential cell to the second power supply.

10. The apparatus of claim 9, further comprising:

a plurality of switches coupled between the source of the differential cell and the current control;

each of the plurality of switches receiving a different signal, and

at least one of the different signals has a different phase than the remaining signals.

12. The apparatus of claim 9, further comprising:

a capacitance coupled to each leg of the differential cell forming an RLC network.

15. The apparatus of claim 9, further comprising:

a current mirror coupled to the single switch that adjusts a current flow through the single switch.

11. The apparatus of claim 11, whereby

the load is a series coupling of a resistor and a series peaking inductor.

13. The apparatus of claim 13, whereby

the capacitance value can be electrically adjusted.

14. The apparatus of claim 14, whereby

an impedance of the series peaking inductor matches a magnitude of the electrically adjusted impedance of the capacitor.

16. The apparatus of claim 16, whereby

the current flow adjusts the characteristics of the resonant RLC network.

17. A divide by 2 apparatus comprising:

a clocked master differential amplifier with first balanced inputs and first balanced output leads;

a complimentary clocked master memory storage unit with a first balanced memory leads coupled to the first balanced output leads;

a complimentary clocked slave differential amplifier with second balanced inputs coupled to the first balanced memory leads;

the complimentary clocked slave differential amplifier with second balanced output leads;

a clocked slave memory storage unit with a second balanced memory leads coupled to the second balanced output leads; and

the second balanced memory leads cross-coupled to the first balanced inputs;

whereby each of the clocked differential amplifiers and memory storage units use two switches in parallel to enabled or disable the differential amplifiers and memory storage units by applying a first high frequency clock to one switch and a second high frequency clock at the same frequency but with a different phase to the other switch.

18. The apparatus of claim 17, whereby

the first and second balanced memory leads provide the divide by 2 clock outputs.

19. The apparatus of claim 17, whereby

the different phase is 90°

.

20. The apparatus of claim 17, whereby

a composite clock is the phasor addition of the two high frequency clocks.