INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION

• US 20130076425A1
• Filed: 03/21/2011
• Published: 03/28/2013
• Est. Priority Date: 06/08/2010
• Status: Abandoned Application

• Current Assignee: Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh, Yohan U. Frans
• Original Assignee: Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh, Yohan U. Frans
• Inventors: Oh, Kyung Suk, Frans, Yohan U., Bansal, Akash, Leibowitz, Brian S.
• Application Number:
  US13/702,261
• Publication Number:
  US 20130076425A1
• Time in Patent Office: Days
• US Class Current: 327/263
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern.

Claims

1. A method of operation of an integrated circuit device, the method comprising:

transmitting, from a first integrated circuit device, a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference;

transmitting, from the first integrated circuit device, a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference; and

generating a timing offset for transmitting data from the first integrated circuit device, wherein the timing offset is derived from information received from a second integrated circuit device sampling the differently-delayed rising edge transitions of the first calibration pattern and the differently-delayed falling edge transitions of the second calibration pattern.

2. The method of claim 1, wherein generating the timing offset comprises:

determining a first timing location with respect to the timing reference based at least on the sampled differently-delayed rising edge transitions;

determining a second timing location with respect to the timing reference based at least on the sampled differently-delayed falling edge transitions;

computing a third timing location by averaging the first timing location and the second timing location; and

generating the timing offset by adding a predetermined phase shift to the third timing location.

3. The method of claim 2,

wherein determining the first timing location comprises locating a first median location within the differently delayed rising edge transitions;

and

wherein determining the second timing location comprises locating a second median location within the differently delayed falling edge transitions.

4. The method of claim 2, wherein the predetermined phase shift is a substantially 90°

phase shift.

5. The method of claim 1, wherein the method further comprises:

transmitting the data delayed by the timing offset from the first integrated circuit device to the second integrated circuit device; and

sampling the data at the second integrated circuit device with a clock signal, wherein clock transitions in the clock signal are aligned to be substantially in a center of a data bit in the data.

6. The method of claim 1, wherein the second calibration pattern is a phase-inverted version of the first calibration pattern.

7. The method of claim 1, wherein the first calibration pattern and the second calibration pattern are the same calibration pattern.

8. The method of claim 1, wherein the first integrated circuit device is a memory controller device and the second integrated circuit device is a memory device.

9. An integrated circuit device, comprising:

an interface to transmit first and second calibration patterns, the first calibration pattern having differently delayed rising edge transitions with respect to a timing reference and the second calibration pattern having differently delayed falling edge transitions with respect to the timing reference; and

a circuit to generate a timing offset for transmitting data to a second integrated circuit device, wherein the timing offset is derived from information received from the second integrated circuit device sampling the first calibration pattern and the second calibration pattern.

10. The integrated circuit device of claim 9, wherein the information includes rising edge samples of the differently delayed rising edge transitions and falling edge samples of the differently delayed falling edge transitions, the integrated circuit device further comprising:

a first circuit to determine a first timing location with respect to the timing reference based at least on the rising edge samples and to determine a second timing location with respect to the timing reference based at least on the falling edge samples;

the first circuit to compute a third timing location by averaging the first timing location and the second timing location; and

the first circuit to generate the timing offset by adding a predetermined phase shift to the third timing location.

11. The integrated circuit device of claim 10, wherein the first circuit further determines the first timing location by locating a first median location within the differently delayed rising edge transitions, and determines the second timing location by locating a second median location within the differently delayed falling edge transitions.

12. The integrated circuit device of claim 10, wherein the predetermined phase shift is a substantially 90°

phase shift.

13. The integrated circuit device of claim 9,

wherein the interface transmits the data delayed by the timing offset to the second integrated circuit device;

and

wherein the second integrated circuit device samples the data delayed by the timing offset using a clock signal, such that the timing offset delays the data to be substantially center aligned with edge transitions in the clock signal.

14. The integrated circuit device of claim 9, wherein the second calibration pattern is a phase-inverted version of the first calibration pattern.

15. The integrated circuit device of claim 9, wherein the first calibration pattern and the second calibration pattern are the same calibration pattern.

16. The integrated circuit device of claim 9, wherein the integrated circuit device is a memory controller device and the second integrated circuit device is a memory device.

17. A method of operation of an integrated circuit device, the method comprising:

sampling a first calibration pattern, having rising edge transitions, in response to differently delayed versions of a timing reference;

sampling a second calibration pattern, having falling edge transitions, in response to differently delayed versions of the timing reference; and

generating a timing offset for sampling data, wherein the timing offset is obtained based at least on information derived from sampling the first calibration pattern and the second calibration pattern.

18. The method of claim 17, wherein generating the timing offset comprises:

determining a first timing location within the rising edge transitions of the first calibration pattern based at least on the information;

determining a second timing location within the falling edge transitions of the second calibration pattern based at least on the information;

computing a third timing location by averaging the first timing location and the second timing location; and

generating the timing offset by adding a predetermined phase shift to the third timing location.

19. The method of claim 18,

wherein determining the first timing location comprises locating a first median location within the rising edge transitions;

and

wherein determining the second timing location comprises locating a second median location within the falling edge transitions.

20. The method of claim 18, wherein the predetermined phase shift is a substantially 90°

phase shift.

21. The method of claim 17, wherein the method further comprises sampling the data using a clock signal derived from a timing reference and the timing offset, such that the timing offset aligns a transition in the clock signal to be substantially in a center of a data bit in the data.

22. The method of claim 17, wherein the second calibration pattern is a phase-inverted version of the first calibration pattern.

23. The method of claim 17, wherein the first calibration pattern and the second calibration pattern are the same calibration pattern.

24. The method of claim 17, wherein the integrated circuit device is a memory controller device.

25. An integrated circuit device, comprising:

an interface to sample;

a first calibration pattern in response to differently delayed versions of a timing reference; and

a second calibration pattern in response to differently delayed versions of the timing reference; and

a circuit to generate a timing offset for sampling data, wherein the timing offset is obtained based at least on information derived from sampling the first calibration pattern and the second calibration pattern.

26. The integrated circuit device of claim 25, wherein the circuit:

determines a first timing location within the rising edge transitions of the first calibration pattern based at least on the information;

determines a second timing location within the falling edge transitions of the second calibration pattern based at least on the information;

computes a third timing location by averaging the first timing location and the second timing location; and

generates the timing offset by adding a predetermined phase shift to the third timing location.

27. The integrated circuit device of claim 26, wherein the circuit determines the first timing location by locating a first median location within the rising edge transitions, and determines the second timing location by locating a second median location within the falling edge transitions.

28. The integrated circuit device of claim 26, wherein the predetermined phase shift is a substantially 90°

phase shift.

29. The integrated circuit device of claim 25, wherein the second calibration pattern is a phase-inverted version of the first calibration pattern.

30. The integrated circuit device of claim 25, wherein the first calibration pattern and the second calibration pattern are the same calibration pattern.

31. The integrated circuit device of claim 25, wherein the integrated circuit device is a memory controller device.