PIXEL GUARD LINES AND MULTI-GATE LINE CONFIGURATION

• US 20130076720A1
• Filed: 09/23/2011
• Published: 03/28/2013
• Est. Priority Date: 09/23/2011
• Status: Abandoned Application

• Current Assignee: Apple Inc.
• Original Assignee: Ahmad Al-Dahle
• Inventors: Yao, Wei Hsin, AL-DAHLE, Ahmad
• Application Number:
  US13/243,938
• Publication Number:
  US 20130076720A1
• Time in Patent Office: Days
• US Class Current: 345/212
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0452 Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0242 Compensation of deficiencies in the appearance of colours
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Data can be written to a sub-pixel by applying a voltage to the sub-pixel'"'"'s data line. A large change in voltage on a data line can affect the voltages on adjacent data lines due to capacitive coupling between data lines. The resulting change in voltage on these adjacent data lines can give rise to visual artifacts in the data lines'"'"' corresponding sub-pixels. Various embodiments of the present disclosure serve to prevent or reduce the appearance of these visual artifacts by inserting guard lines between data lines to reduce the mutual capacitance between data lines. In other embodiments, a pixel having multiple gate lines can be used to selectively turn on and turn off different sub-pixels which, in turn, can reduce or eliminate the appearance of visual artifacts.

Claims

1. A display apparatus, comprising:

an array of pixels, each pixel associated with a plurality of sub-pixels, each sub-pixel associated with a data line;

a display driver that sequentially applies voltage to the data lines in each pixel in accordance with a write sequence; and

a plurality of electrically conductive guard lines, each guard line positioned between two adjacent data lines.

2. The display apparatus of claim 1, wherein each guard line is connected to a reference potential.

3. The display apparatus of claim 2, wherein the reference potential is connected to ground or AC ground.

4. The display apparatus of claim 1, wherein the adjacent data lines belong to the same pixel.

5. The display apparatus of claim 1, wherein the adjacent data lines include a first data line and a second data line, the first and second data lines each belonging to a different pixel.

6. The display apparatus of claim 1, wherein the display apparatus is integrated within a computing system.

7. A method for displaying an image on a display apparatus having an array of pixels, each pixel associated with a plurality of sub-pixels, each sub-pixel associated with a data line, the method comprising:

sequentially applying a voltage to the data lines in the pixel in accordance with a write sequence; and

shielding electric field lines between two adjacent data lines with an electrically conductive guard line positioned between the adjacent data lines.

8. The method of claim 7, further comprising connecting each guard line to a reference potential.

9. The method of claim 8, wherein the reference potential is connected to ground or AC ground.

10. The method of claim 7, wherein the adjacent data lines belong to the same pixel.

11. The method of claim 7, wherein the adjacent data lines include a first data line and a second data line, the first and second data lines each belonging to a different pixel.

12. A display apparatus, comprising:

an array of pixels, each pixel associated with one of a plurality of data lines, each pixel including a plurality of sub-pixels, each sub-pixel associated with a gate line and including a pixel TFT connected to the data line and to the gate line;

a timing control module configured to generate a control signal, the control signal identifying a sub-pixel to be turned on and a plurality of sub-pixels to be turned off; and

a gate driver configured to selectively apply a voltage to a gate line of the sub-pixel to be turned on based on the control signal,

wherein a pixel TFT of the sub-pixel to be turned on is electrically connected to the data line, and

wherein pixel TFTs of the plurality of sub-pixels to be turned off are electrically disconnected from the data line.

13. The display apparatus of claim 12, further comprising a plurality of source amplifiers, individual ones of the source amplifiers connected to different ones of the plurality of data lines, each source amplifier applying a voltage to the data line in accordance with a write sequence.

14. The display apparatus of claim 13, wherein each source amplifier applies a voltage to the data line at substantially the same time.

15. The display apparatus of claim 12, wherein the control signal is a clock pulse.

16. The display apparatus of claim 12, wherein each sub-pixel further includes a liquid crystal capacitor having a pixel electrode and a common electrode.

17. The display apparatus of claim 16, wherein the pixel electrode is connected to the pixel TFT.

18. The display apparatus of claim 12, wherein the pixel TFT is connected to the data line via a data line extension.

19. The display apparatus of claim 12, wherein the pixel is associated with only a single data line.

20. The display apparatus of claim 12, wherein the display apparatus is integrated within a computing system.

21. A method for displaying an image on a display apparatus having an array of pixels, each pixel associated with one of a plurality of data lines, each pixel including a plurality of sub-pixels, each sub-pixel associated with a gate line and including a pixel TFT connected to the data line and to the gate line, the method comprising:

generating a control signal, the control signal identifying a sub-pixel to be turned on and a plurality of sub-pixels to be turned off; and

selectively applying a voltage to a gate line of the sub-pixel to be turned on based on the control signal,

wherein a pixel TFT of the sub-pixel to be turned on is electrically connected to the data line, and

wherein pixel TFTs of the plurality of sub-pixels to be turned off are electrically disconnected from the data line.

22. The method of claim 21, further comprising applying voltages to the data lines in accordance with a write sequence.

23. The method of claim 22, wherein the voltages are applied to the data lines at substantially the same time.