Dual Pixel Pitch Imaging Array with Extended Dynamic Range

• US 20130076910A1
• Filed: 09/24/2012
• Published: 03/28/2013
• Est. Priority Date: 09/22/2011
• Status: Active Grant

• Current Assignee: Basil Henry Scott, Mavourneen Wilcox, Porfirio A. Dubon
• Original Assignee: Basil Henry Scott
• Inventors: Scott, Basil Henry
• Granted Patent: US 8,970,706 B2
• Time in Patent Office: Days
• US Class Current: 348/164
• CPC Class Codes: H03K 5/125 Discriminating pulses measuring characteristics of individual pulses G01R29/02; separation of synchronising signals in television systems H04N5/08
• CPC Class Codes: H04N 23/11 for generating image signals from visible and infrared light wavelengths
• CPC Class Codes: H04N 25/42 by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
• CPC Class Codes: H04N 25/702 SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout

Abstract

An integrated focal plane provides two co-aligned, overlapping pixel arrays in two formats, one with large pixels and low pixel count, the other with small pixels and high pixel count. Typically, the large pixels are 10 to 100 times larger in area than the small pixels. The dual arrays are disposed in a single detector substrate flip-chip bonded to a single readout circuit. They are sensitive to two infrared colors, one shorter and one longer wavelength band. The dual array focal plane concurrently provides two distinct pixel instantaneous fields of view within the same overall field of view as well as simultaneous fast and slow frame rates. The dual frame rates allow for combined fast sensing with sensitive imaging. Differing spatial and temporal data enables enhanced image processing for improved clutter rejection and detection performance. Differing gains combined with the dual frame rates provide an extended dynamic range.

Claims

1. A focal plane imaging array having a dynamic range, comprising:

a detector with a large pixel array having a plurality of large pixels, each of said large pixels having a large pixel area and a large pixel signal contact, to create a first signal that travels to said large pixel signal contact, and a small pixel array having a plurality of small pixels, each of said small pixels having a small pixel area and a small pixel signal contact, to create a second signal that travels to said small pixel signal contacts, wherein said plurality of small pixels is larger than said plurality of large pixels, wherein said large pixel array and said small pixel array are aligned and vertically stacked on a monolithic semiconductor substrate;

a readout integrated circuit operably interconnected to said large pixel signal contacts and said small pixel signal contacts; and

a clock operably connected to said large pixel signal contacts and said small pixel signal contacts to read said first signals at a first clock rate having a first integration time and a first reset time, and to read said second signals at a second clock rate having a second integration time and a second reset time;

wherein said first clock rate is faster than said second clock rate;

whereby reading of said first signals at said first clock rate, and said second signals at said second clock rate, extends said dynamic range.

2. A focal plane imaging array according to claim 1, wherein said large pixel area is at least twice as large as said small pixel area.

3. A focal plane imaging array according claim 1, wherein said first clock rate is at least 1500 frames per second.

4. A focal plane imaging array according claim 1, wherein said second clock rate is no more than 500 frames per second.

5. A focal plane imaging array according to claim 1, further comprising a wide band gap barrier between said large pixel array and said small pixel array to prevent crosstalk between said large pixels and said small pixels.

6. A focal plane imaging array according claim 1, wherein said large pixels are responsive to a first brightness range, and said small pixels are responsive to a second brightness range, and wherein said first brightness range is different from said second brightness range.

7. A focal plane imaging array according to any one of claim 1, 2, 3, 4, 5, or 6, wherein said readout integrated circuit further comprises:

a large pixel amplifier having an electrical gain for receiving said first signal and creating a large pixel output voltage;

a large pixel comparator to receive said large pixel output voltage;

wherein when said large pixel output voltage indicates that said large pixel is saturated, said large pixel comparator outputs a TRUE value that changes said first clock rate to have a first changed integration time and a first changed reset time, wherein said first changed integration time is shorter than said first integration time and said first changed reset time is greater than said first reset time, and wherein if said large pixel output voltage indicates that said large pixel is unsaturated, said large pixel comparator outputs a FALSE value and said first clock rate maintains said first integration time and said first reset time;

a plurality of small pixel amplifiers for receiving said second signal and creating small pixel output voltages; and

a small pixel comparator to receive said small pixel output voltages;

wherein when said small pixel output voltages indicate that a preset number of small pixels are saturated, said small pixel comparator outputs a TRUE value that changes said second clock rate to have a second changed integration time and a second changed reset time, wherein said second changed integration time is less than said second integration time and said second changed reset time is greater than said second reset time, and wherein if said small pixel output voltages indicate that said small pixels are unsaturated, said small pixel comparator outputs a FALSE value and said second clock rate maintains said second integration time and said second reset time;

wherein if said small pixel output voltages indicate that a preset number of said small pixels are saturated while using said second changed integration time and a second changed reset time, said small pixel comparator will output another TRUE value that changes said second clock rate so that it has a second re-changed integration time and a second re-changed reset time, wherein said second re-changed integration time is shorter than said second changed integration time and said second re-changed reset time is longer than said second changed reset time, and wherein if said small pixel output voltages indicate that said small pixels are unsaturated while using said second changed integration time and a second changed reset time, said small pixel comparator will output a FALSE value and said second clock rate will remain at said second changed integration time and said second changed reset time;

whereby the reading of said first signals at said first changed integration time, and said second signals at said second changed integration time and said second re-changed integration time, extends said dynamic range.

8. A focal plane imaging array according to claim 7, further comprising:

a master frame reset clock to send a small pixel reset signal, which causes said second changed integration time and second changed reset time to return to said second integration time and said second reset time, and causes said second re-changed integration time and said second re-changed reset time to return to said second integration time and said second reset time.

9. A focal plane imaging array according to claim 7, wherein said second reset time, said second change reset time, or said second re-changed reset time, causes a large pixel reset signal which changes said first changed integration time and said first changed reset time to said first integration time and first reset time.

10. A focal plane imaging array according to claim 7, wherein said large pixel amplifier further comprises:

a first integration capacitor for storing said first signal and producing said large pixel output voltage; and

a second integration capacitor for storing said first signal;

wherein if said large pixel output voltage is saturated, said second integration capacitor is turned on to reduce said electrical gain, and if said large pixel output voltage is unsaturated, said second integration capacitor is turned off.

11. A focal plane imaging array according to claim 1, wherein said large pixels absorb a first wavelength and said small pixels absorb a second wavelength.

13. A focal plane imaging array according to claim 7, wherein said small pixel comparator comprises a capacitor averaging comparator for comparing a plurality of pixel electrical signals, each having a signal voltage, further comprising:

a plurality of signal switches, each signal switch corresponding to one of said pixel electrical signals;

a buffer amplifier connected to said signal switches;

a first capacitor;

a first capacitor switch connected between said buffer amplifier and said first capacitor;

a second capacitor;

a second capacitor switch connected between said first capacitor and said second capacitor; and

a latching comparator connected to said second capacitor controlled by a comparator control voltage;

wherein when said signal switches are sequentially closed, each of said pixel electrical signals is sequentially sent to said buffer amplifier, said first capacitor switch is closed, said buffer amplifier drives said first capacitor to store a first stored voltage that is proportional to said signal voltage, said first capacitor switch opens, said second capacitor switch closes and charge is transferred between said first and second capacitors, causing any prior stored voltage on said second capacitor and said first stored voltage on said first capacitor to form a weighted average voltage, and said comparator compares said weighted average voltage to said comparator control voltage;

wherein said weighted average is based on the ratio of capacitance between said first capacitor and said second capacitor, and

wherein if any of said weighted average voltages exceeds said comparator control voltage, then said comparator latches to a high value.

12. A capacitor averaging comparator for comparing a plurality of pixel electrical signals, each having a signal voltage comprising:

a plurality of signal switches, each signal switch corresponding to one of said pixel electrical signals;

a buffer amplifier connected to said signal switches;

a first capacitor;

a first capacitor switch connected between said buffer amplifier and said first capacitor;

a second capacitor;

a second capacitor switch connected between said first capacitor and said second capacitor; and

a latching comparator connected to said second capacitor controlled by a comparator control voltage;

wherein when said signal switches are sequentially closed, each of said pixel electrical signals is sequentially sent to said buffer amplifier, said first capacitor switch is closed, said buffer amplifier drives said first capacitor to store a first stored voltage that is proportional to said signal voltage, said first capacitor switch opens, said second capacitor switch closes and charge is transferred between said first and second capacitors, causing any prior stored voltage on said second capacitor and said first stored voltage on said first capacitor to form a weighted average voltage, and said comparator compares said weighted average voltage to said comparator control voltage;

wherein said weighted average is based on the ratio of capacitance between said first capacitor and said second capacitor, and

wherein if any of said weighted average voltages exceeds said comparator control voltage, then said comparator latches to a high value.

14. A process for using a focal plane imaging array having a background brightness and a detector operably connected to a readout circuit having a large pixel array having a plurality of large pixels, each of said large pixels having a large pixel area and a large pixel signal contact, to absorb a first wavelength, and a small pixel array having a plurality of small pixels, each of said small pixels having a small pixel area and a small pixel signal contact, to absorb a second wavelength, wherein said plurality of small pixels is greater than said plurality of large pixels, and wherein said large pixel array and said small pixel array are aligned and vertically stacked on a monolithic semiconductor substrate, comprising:

illuminating said large pixel array and small pixel array with an infrared light source to create a first signal that travels to said large pixel signal contacts, and a second signal that travels to said small pixel signal contacts;

clocking said first signal at a first clock rate having a first integration time and a first reset time, and said second signal at a second clock rate having a second integration time and a second reset time, wherein said first clock rate is faster than said second clock rate; and

shortening said first integration time if said first signal saturates said large pixels between said first rest times, and reducing said second integration time if said second signal saturates said small pixels between said second reset times;

whereby said process achieves extended dynamic range and better clutter rejection for said focal plane array.

15. The process of claim 14, further comprising:

determining an average for said background brightness;

processing said first signal to detect fast events having a fast event brightness that occurs within a time range, and said second signal to detect standard events having a standard event brightness, wherein said fast event brightness is comprised of said background brightness and an actual fast event brightness, and said standard event brightness is comprised of said background brightness and an actual standard event brightness;

calculating said actual fast event brightness and said actual standard event brightness;

comparing said actual fast event brightness and said actual standard event brightness to approximate a temperature range for said fast events and said standard events; and

determining whether said fast events and said standard events are threatening based on said temperature range.

16. The process of claim 15, wherein said calculating step further comprises:

determining a spatial correction factor for said fast event brightness based on the spatial extent of said standard event brightness, and a temporal correction factor for said standard event brightness based on the duration of said fast event brightness;

correcting said background brightness using said spatial correction factor to achieve a spatially corrected background brightness, and using said temporal correction factor to achieve a temporally corrected background brightness; and

subtracting said spatially corrected background brightness from said fast event brightness to achieve said actual fast event brightness, and subtracting said temporally corrected background brightness from said standard event brightness to achieve said actual fast event brightness.