SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME

• US 20130077392A1
• Filed: 12/15/2011
• Published: 03/28/2013
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Hae Chan, Kim, Soo Gil
• Granted Patent: US 8,780,621 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/00 Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor G11C14/00 - G11C21/00 take precedence
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: Y10S 977/754 Dendrimer, i.e. serially branching or "tree-like" structure

Abstract

A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

Claims

1. A semiconductor integrated circuit system, comprising:

a memory cell array including a plurality of word lines, a plurality of bit lines crossing the plurality of word lines, and a phase-change memory cell formed on each of intersections of the plurality of word lines and the plurality of bit lines;

a reset current unit configured to apply a reset current to a bit line of the bit lines to control one selected from among the phase-change memory cells to have a amorphous state;

a set current unit configured to apply a set current to a bit line of the bit lines to control one selected from the phase-change memory cells to have a crystalline state; and

a phase-change compensation unit configured to apply a correction current to a memory cell adjacent to each of the selected phase-change memory cells through a word line of the adjacent memory cell to compensate for a phase-change of the adjacent memory cell.

2. The semiconductor integrated circuit system of claim 1, wherein the correction current has a smaller magnitude than the set current and the reset current.

3. The semiconductor integrated circuit system of claim 1, wherein the correction current has a magnitude for compensating for a phase-change of the adjacent memory cell without affecting phase-changes of memory cells adjacent to the adjacent memory cell.

4. The semiconductor integrated circuit system of claim 1, wherein the correction current is applied as a signal pulsed at least once in a write enable period of the selected memory cell.

5. The semiconductor integrated circuit system of claim 1, wherein the correction current is applied as a signal pulsed at least once immediately after a write enable period of the selected memory cell is ended.

6. The semiconductor integrated circuit system of claim 1, wherein the phase-change compensation unit includes:

a resistance detection unit configured to detect a resistance of a phase-change area of the adjacent memory cell; and

a current generation unit configured to determine an amount of the correction current in response to a detection result of the resistance detection unit.

7. The semiconductor integrated circuit system of claim 1, wherein the selected memory cell and the adjacent memory cell share common phase-change line.

8. A semiconductor integrated circuit system, comprising:

a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell;

a write current providing unit configured to phase-change a selected one of the first and second phase-change areas; and

a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area.

9. The semiconductor integrated circuit system of claim 8, wherein phase-change compensation unit is configured to provide a correction current to compensate for the dummy phase-change.

10. The semiconductor integrated circuit system of claim 9, wherein the write current providing unit includes:

a reset current unit configured to provide a reset current to control the first and second phase-change areas to have an amorphous state; and

a set current unit configured to provide a set current to control the first and second phase-change areas to have a crystalline state.

11. The semiconductor integrated circuit system of claim 10, wherein each of the first and second memory cells includes a word line and a bit line.

12. The semiconductor integrated circuit system of claim 11, wherein the set current and the reset current are provided to the bit line, and the correction current is provided through the word line.

13. The semiconductor integrated circuit system of claim 12, wherein the correction current has a smaller magnitude than the set current and the reset current.

14. The semiconductor integrated circuit system of claim 12, wherein the correction current is provided as a signal pulsed at least once within a write enable period of the one of the first and second memory cells.

15. The semiconductor integrated circuit system of claim 12, wherein the correction current is provided as a signal pulsed at least once immediately after a write enable period of the one of the first and second memory cells is terminated.

16. The semiconductor integrated circuit system of claim 9, wherein the phase-change compensation unit includes:

a resistance detection unit configured to detect a resistance of the other of the first and second phase-change areas; and

a current generation unit configured to determine an amount of the correction current in response to a detection result of the resistance detection unit.

17. A method of driving a semiconductor integrated circuit system, comprising:

phase-changing a selected memory cell area to a reset state;

detecting a phase-change resistance of a memory cell area adjacent to the selected memory cell area on the same phase-change line;

generating a correction current in response to a detection result of the phase-change resistance of the adjacent memory cell area; and

maintaining a phase-change state of the adjacent memory cell area by applying the correct current to the adjacent memory cell area.

18. The method of claim 17, wherein the phase-changing of the selected memory cell area includes applying a set current or a reset current to a bit line constituting the selected memory cell area.

19. The method of claim 17, wherein the applying of the correction current includes applying the correction current to a word line constituting the adjacent memory cell area.

20. The method of claim 19, wherein the correction current is applied as a signal pulsed at least once within a write enable period of the selected memory cell.

21. The method of claim 19, wherein the correction current is applied as a signal pulsed at least once immediately after a write enable period of the selected memory cell is terminated.