SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

• US 20130077399A1
• Filed: 12/30/2011
• Published: 03/28/2013
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KANG, Won Kyung
• Granted Patent: US 9,058,900 B2
• Time in Patent Office: Days
• US Class Current: 365/185.2
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A method for operating a semiconductor memory device including a memory block constituted by first memory cells used as main memory cells and second memory cells includes reading out an erase count of the memory block stored in the second memory cells, erasing the memory block, increasing the read-out erase count, and storing the increased erase count in the second memory cells.

Claims

1. A method for operating a semiconductor memory device including a memory block constituted by first memory cells used as main memory cells and second memory cells, the method comprising:

reading out an erase count of the memory block stored in the second memory cells, erasing the memory block, increasing the read-out erase count, and storing the increased erase count in the second memory cells.

2. The method according to claim 1, wherein the second memory cells comprise dummy memory cells.

3. The method according to claim 2,

wherein the main memory cells and the dummy memory cells are divided into a main cell area and a flag cell area,

wherein the erase count of the memory block is read out from the flag cell area of the dummy memory cells, and

wherein the increased erase count is stored in the flag cell area of the dummy memory cells.

4. The method according to claim 3, wherein error check is performed for data which are read out from the flag cell area of the main memory cells and the flag cell area of the dummy memory cells.

5. The method according to claim 4, wherein the error check includes majority check in which majority data among the read-out data are determined as effective data.

6. The method according to claim 4, wherein the erase count read out from the flag cell area of the dummy memory cells is provided to an external device in response to a request from the external device.

7. The method according to claim 3, wherein whether or not upper bits of the main memory cells are programmed is stored in the flag cell area of the main memory cells.

8. The method according to claim 1, wherein the second memory cells are hidden areas which cannot be accessed by a user.

9. A semiconductor memory device comprising:

a memory block including first memory cells used as main memory cells and second memory cells; and

a control logic configured to control an erase operation of the memory block,

wherein the control logic reads out an erase count of the memory block stored in the second memory cells, erases the memory block, increases the read-out erase count, and stores the increased erase count to the second memory cells.

10. The semiconductor memory device according to claim 9, further comprising:

a data input/output circuit configured to store data in the first memory cells and the second memory cells and read out data from the first memory cells and the second memory cells;

a counter configured to increase the erase count; and

a register configured to temporarily store the increased erase count.

11. The semiconductor memory device according to claim 10, wherein the second memory cells comprise dummy memory cells.

12. The semiconductor memory device according to claim 11

wherein the main memory cells and the dummy memory cells are divided into a main cell area and a flag cell area, and

wherein the data input/output circuit reads out the erase count of the memory block from the flag cell area of the dummy memory cells under the control of the control logic and provides the read-out erase count to the counter.

13. The semiconductor memory device according to claim 12, wherein the data input/output circuit stores the increased erase count provided from the register, in the flag cell area of the dummy memory cells under the control of the control logic.

14. The semiconductor memory device according to claim 12, wherein the data input/output circuit stores whether or not upper bits of the main memory cells are programmed, to the flag cell area of the main memory cells under the control of the control logic.

15. The semiconductor memory device according to claim 9, wherein the second memory cells are hidden areas which cannot be accessed by a user.

16. A system comprising:

a memory block including first memory cells used as main memory cells and second memory cells; and

a control logic configured to control an erase operation of the memory block,

wherein the control logic reads out an erase count of the memory block stored in the second memory cells, erases the memory block, increases the read-out erase count, and stores the increased erase count to the second memory cells.

17. The system according to claim 16, further comprising:

a data input/output circuit configured to store data in the first memory cells and the second memory cells and read out data from the first memory cells and the second memory cells;

a counter configured to increase the erase count; and

a register configured to temporarily store the increased erase count.

18. The system according to claim 17, wherein the second memory cells comprise dummy memory cells.

19. The system according to claim 18

wherein the main memory cells and the dummy memory cells are divided into a main cell area and a flag cell area, and

wherein the data input/output circuit reads out the erase count of the memory block from the flag cell area of the dummy memory cells under the control of the control logic and provides the read-out erase count to the counter.

20. The system according to claim 19, wherein the data input/output circuit stores the increased erase count provided from the register, in the flag cell area of the dummy memory cells under the control of the control logic.