ROW DRIVER CIRCUIT FOR NAND MEMORIES INCLUDING A DECOUPLING INVERTER

• US 20130077412A1
• Filed: 09/26/2011
• Published: 03/28/2013
• Est. Priority Date: 09/26/2011
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Sivero, Stefano
• Granted Patent: US 8,625,358 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

Devices and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.

Claims

1. A device for driving appropriate voltages to a memory array, the device comprising:

a reference potential node supplied with a reference potential;

first, second, third and fourth nodes;

a first transistor having a source-drain path coupled between the first and second nodes and a gate coupled to the third node;

a second transistor having a source-drain path coupled between the first and third nodes and a gate coupled to the second node;

a third transistor having a source-drain path coupled between the third node and the reference potential node and a gate coupled to the second node;

a fourth transistor having a source-drain path coupled between the first and fourth nodes and a gate coupled to the second node; and

a fifth transistor having a source-drain path coupled between the fourth node and the reference potential node and a gate coupled to the second node.

2. The device as claimed in claim 1, wherein the second node is configured to change in level between the reference potential and a first potential that is greater than the reference potential, and the first node is configured to change in level between the first potential and a second potential that is greater than the first potential.

3. The device as claimed in claim 2, wherein the first node changes from the first potential to the second potential when or after the second node takes the reference potential.

4. The device as claimed in claim 3, wherein the first node returns from the second potential to the first potential during the second taking the reference potential.

5. The device as claimed in claim 1, wherein each of the first, second and fourth transistor is of a first channel type and each of the third and fifth transistors is of a second channel type.

6. The device as claimed in claim 3, wherein each of the first, third and fifth transistors is rendered conductive and the each of the second and fourth transistors is rendered non-conductive when the second node takes the reference potential.

7. The device as claimed in claim 6, wherein the third and fourth nodes are changed toward the second potential through the second and fourth transistors, respectively, when the first node changes to the second potential.

8. The device as claimed in claim 1, further comprising a sixth transistor and a fifth node, the fifth transistor having a source-drain path coupled between the second node and the fifth node and a gate supplied with the first potential, the fifth node being connected in common to the source-drain path of the first transistor and the gates of the second, fourth and fifth transistors.

9. The device as claimed in claim 2, further comprising a capacitor having a first end coupled to the fourth end and a second end supplied with a boosting signal.

10. The device as claimed in claim 9, further comprising a fifth transistor having a source-drain path inserted between the fourth node and the capacitor and a gate supplied with a control signal.

11. The device as claimed in claim 10, wherein the control signal changes in level between the first potential and a third potential that is greater than the second potential.

12. The device as claimed in claim 11, wherein the control signal changes from the first potential toward the third potential prior to the first node changing from the first potential toward the second potential.

13. A device comprising:

a non-volatile memory cell coupled to a word line; and

a word line driver driving the word line to a selection level, the word line driver comprising;

a reference potential node supplied with a reference potential;

first, second, third and fourth nodes;

a first transistor having a source-drain path coupled between the first and second nodes and a gate coupled to the third node;

a second transistor having a source-drain path coupled between the first and third nodes and a gate coupled to the second node;

a third transistor having a source-drain path coupled between the third node and the reference potential node and a gate coupled to the second node;

a fourth transistor having a source-drain path coupled between the first and fourth nodes and a gate coupled to the second node;

a fifth transistor having a source-drain path coupled between the fourth node and the reference potential node and a gate coupled to the second node;

a capacitor having a first end coupled to the fourth node and a second end supplied with a boosting signal;

a voltage line supplied with the selection level; and

a sixth transistor having a source-drain path coupled between the word line and the voltage line and a gate coupled to the first end of the capacitor.

14. The device as claimed in claim 13, wherein the word line driver further comprises a seventh transistor having a source-drain path inserted between the fourth node and the first end of the capacitor and a gate supplied with a control signal.

15. The device as claimed in claim 13, wherein the second node is configured to change in level between the reference potential and a first potential that is greater than the reference potential, and the first node is configured to change in level between the first potential and a second potential that is greater than the first potential.

16. The device as claimed in claim 15, wherein the first node changes from the first potential to the second potential when the second takes the reference potential.

17. The device as claimed in claim 16, wherein the first node returns from the second potential to the first potential during the second taking the reference potential.

18. The device as claimed in claim 17, wherein the boosting signal changed from an initial level to a boosting level during the first node taking the second potential.

19. The device as claimed in claim 18, wherein the boosting signal returns from the boosting level to the initial level during the first node taking the second potential.