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ROW DRIVER CIRCUIT FOR NAND MEMORIES INCLUDING A DECOUPLING INVERTER

  • US 20130077412A1
  • Filed: 09/26/2011
  • Published: 03/28/2013
  • Est. Priority Date: 09/26/2011
  • Status: Active Grant
First Claim
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1. A device for driving appropriate voltages to a memory array, the device comprising:

  • a reference potential node supplied with a reference potential;

    first, second, third and fourth nodes;

    a first transistor having a source-drain path coupled between the first and second nodes and a gate coupled to the third node;

    a second transistor having a source-drain path coupled between the first and third nodes and a gate coupled to the second node;

    a third transistor having a source-drain path coupled between the third node and the reference potential node and a gate coupled to the second node;

    a fourth transistor having a source-drain path coupled between the first and fourth nodes and a gate coupled to the second node; and

    a fifth transistor having a source-drain path coupled between the fourth node and the reference potential node and a gate coupled to the second node.

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