Systems, Circuits and Methods for Time Stamp Based One-Way Communications

• US 20130077641A1
• Filed: 09/22/2011
• Published: 03/28/2013
• Est. Priority Date: 09/22/2011
• Status: Abandoned Application

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Harley F. Burger Jr
• Inventors: Burger, Harley F. Jr.
• Application Number:
  US13/241,047
• Publication Number:
  US 20130077641A1
• Time in Patent Office: Days
• US Class Current: 370/474
• CPC Class Codes: G08C 17/02 using a radio link
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 9/3297 involving time stamps, e.g. generation of time stamps

Abstract

A circuit includes an input terminal for receiving an input signal and a time stamp circuit including an input and an output. The input is coupled to the input terminal. The time stamp circuit includes a timer, and the output is for providing a time stamp based on a value of the timer in response to receiving the input signal. The circuit further includes an encoder including an input coupled to the output of the time stamp circuit and configured to encode the time stamp into a packet. The circuit also includes a transmitter configured to transmit the packet.

Claims

1. An apparatus comprising:

an input terminal for receiving an input signal;

a time stamp circuit having an input coupled to the input terminal, the time stamp circuit including a timer and having an output for providing a time stamp based on a value of the timer in response to receiving the input signal;

an encoder including an input coupled to the output of the time stamp circuit and configured to encode the time stamp into a packet; and

a transmitter configured to transmit the packet.

2. The apparatus of claim 1, wherein the encoder encrypts the time stamp before encoding the time stamp into the payload portion.

3. The apparatus of claim 1, wherein the timer comprises:

a first latch including a data input, a clock input for receiving a clock signal, and an output;

a summing node including a node input and a node output and configured to increment a value at the node input and to provide the incremented value to the node output, the node input coupled to the output of the first latch, the node output coupled to the data input of the first latch; and

a second latch including a data input coupled to the output of the first latch, a clock input coupled to the input terminal, and the output for providing the time stamp.

4. The apparatus of claim 1, wherein the timer comprises:

a first timer configured to generate a first timer output;

a second timer to generate second timer output having a pre-determined offset; and

wherein the time stamp is derived from the first and second timer outputs.

5. The apparatus of claim 4, further comprising:

a first memory to store the first timer output in response to the input signal from the input terminal;

a second memory to store the second timer output periodically; and

wherein;

a first write frequency of the volatile timer that is associated with writing the first timer output to the first memory is greater than a second write frequency of the second timer that is associated with writing the second timer output to the second memory; and

the second timer is configurable to gradually decrease the second write frequency over a period of time.

6. The apparatus of claim 4, wherein the first timer comprises:

a first latch including a data input, a clock input for receiving a clock signal, a reset input, and an output;

a summing node including a node input and a node output, the node input coupled to the output of the first latch, the node output coupled to the data input of the first latch, the summing node configured to increment a value received at the node input and to provide the incremented value to the node output;

a second latch including a data input coupled to the output of the first latch, a clock input coupled to the input terminal, and an output coupled to the second memory; and

a comparator including a first input coupled to the output off the first latch, a second input for receiving a pre-determined threshold, and a comparator output; and

wherein the comparator output is coupled to the reset input of the first latch to reset the time stamp when a signal on the comparator output transitions from a logic low value to a logic high value.

7. The apparatus of claim 6, wherein the second timer comprises:

a third latch circuit including a data input, a clock input, and an output, the clock input coupled to the comparator output; and

a summing node including a node input coupled to the output of the third latch circuit and a node output coupled to the non-volatile memory and to the data input of the third latch circuit, the summing node configured to increment a value at the node input and to provide the incremented value to the node output.

8. A method comprising:

receiving a signal corresponding to a user input at an input terminal of a circuit;

generating a time stamp, using a timer of the circuit, in response to receiving the signal, the time stamp corresponding to a value of the timer when the signal is received;

encoding the time stamp to produce a packet using an encoder of the circuit; and

providing the packet to a communication link via a transmitter of the circuit.

9. The method of claim 8, wherein the method further comprises:

scrambling the time stamp using seed data; and

encrypting the payload of the packet.

10. The method of claim 9, wherein the seed data comprises a portion of an identification number associated with the circuit.

11. The method of claim 8, wherein generating the time stamp comprises:

generating a first time value using a first timer in response to receiving the signal;

combining the first time value with a second time value from a second timer to produce a combined time value; and

selectively truncating bits of one of the first time value and the second time value to produce the time stamp.

12. The method of claim 11, wherein selectively truncating the bits comprises truncating a selected number of least significant bits of the first time value.

13. The method of claim 11, wherein combining the first time value with the second time value comprises appending the first time value to the second time value such that the second time value represents most significant bits of the time stamp.

14. The method of claim 11, further comprises:

generating the second time value using the second timer having an increment frequency that is less than an increment frequency of the first timer; and

decreasing a frequency with which at least one of the first timer and the second timer is incremented over a period of time after receiving the signal.

15. A system comprising:

a transmit device configured to transmit a packet through a wireless link, the packet including an encrypted time stamp, the transmit device comprising;

a transmitter including an input and including an output for transmitting the packet;

an encoder/packet generator including an input for receiving data including a time stamp and an output coupled to the input of the transmitter; and

a time stamp circuit including a timer, the timer stamp circuit configured to generate a time stamp corresponding to a value of the timer in response to an input signal.

16. The system of claim 15, further comprising:

a receiver device configured to receive the packet from the wireless link, to decode the packet to retrieve the time stamp, and to authenticate the packet using the time stamp, the receiver device configured to ignore the packet when the time stamp falls outside of a time stamp window and to operate on the packet when the time stamp falls within the time stamp window; and

wherein the receiver device includes a control logic circuit to initiate a resynchronization process when the time stamp is greater than a previous time stamp but outside of the time stamp window.

17. The system of claim 16, wherein the control logic circuit uses a resynchronization window that is smaller than the time stamp window for receiving a second input signal having a new time stamp that is greater than the time stamp.

18. The system of claim 15, wherein the time stamp circuit comprises:

a first latch including a data input, a clock input for receiving a clock signal, and an output;

a summing node including a node input and a node output, the node input coupled to the output of the first latch, the node output coupled to the data input of the first latch, the summing node configured to increment a value at the node input and to provide the incremented value to the node output; and

a second latch including a data input coupled to the output of the first latch, a clock input coupled to the input terminal, and the output for providing the time stamp.

19. The system of claim 15, wherein the time stamp circuit comprises:

a first timer configured to generate a first timer output;

a second timer to generate a second timer output having a pre-determined offset; and

wherein the second timer output and the first timer output are combined to form the time stamp.

20. The system of claim 19, wherein the transmitter, the encoder/packet generator, and the time stamp circuit are implemented in processor readable instructions and hardware of an integrated circuit, the integrated circuit comprising:

a processor;

a memory accessible to the processor for storing instructions and timer data; and

one or more timers coupled to the processor.