TRANSCEIVERS WITH CONFIGURABLE INTEGRATED CIRCUIT

• US 20130077968A1
• Filed: 09/28/2011
• Published: 03/28/2013
• Est. Priority Date: 09/28/2011
• Status: Active Grant

• Current Assignee: Gigamon Incorporated (Elliott Capital Advisors LP)
• Original Assignee: Gigamon Incorporated (Elliott Capital Advisors LP)
• Inventors: YANG, Yunfa
• Granted Patent: US 9,379,816 B2
• Time in Patent Office: Days
• US Class Current: 398/45
• CPC Class Codes: H04B 10/40 Transceivers

Abstract

A transceiver includes a housing, an optical interface for detachably coupling to an optical transmission device, an optical-electrical conversion unit coupled to the optical interface, the optical-electrical conversion unit located in the housing, a programmable logic device communicatively coupled to the optical-electrical conversion unit, and an electrical interface communicatively coupled to the programmable logic device, wherein the electrical interface is configured for detachably coupling to an electrical transmission device. In some embodiments, the programmable logic device may be configured to perform packet filtering, packet slicing, time stamping, packet analysis, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof.

Claims

1. A transceiver, comprising:

a housing;

an optical interface for detachably coupling to an optical transmission device;

an optical-electrical conversion unit coupled to the optical interface, the optical-electrical conversion unit located in the housing;

a programmable logic device communicatively coupled to the optical-electrical conversion unit; and

an electrical interface communicatively coupled to the programmable logic device, wherein the electrical interface is configured for detachably coupling to an electrical transmission device.

2. The transceiver of claim 1, wherein the programmable logic device is configured to perform packet filtering, packet slicing, time stamping, packet analysis, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof.

3. The transceiver of claim 1, further comprising:

a diagnostic unit located in the housing configured to detect a predetermined condition; and

a port coupled to the diagnostic unit for reporting a detection of the predetermined condition.

4. The transceiver of claim 1, further comprising a first end and a second end, wherein the optical interface and the electrical interface are located at the first end, and the programmable logic device is located at the second end.

5. The transceiver of claim 1, wherein the programmable logic device comprises a clock recovery unit configured to determine time data for time stamping packets received at the transceiver.

6. The transceiver of claim 1, wherein the programmable logic device comprises a memory for storing information associated with a processing of packets received at the transceiver.

7. The transceiver of claim 1, further comprising a local clock unit for providing a reference clock signal.

8. The transceiver of claim 1, further comprising a power management unit coupled to the programmable logic device, wherein the power management is configured to deactivate the transceiver in response to a detected condition.

9. The transceiver of claim 1, further comprising a configuration port for configuring the programmable logic device.

10. The transceiver of claim 1, further comprising an input coupled to the programmable logic device for receiving a clock signal from an external clock.

11. The transceiver of claim 1, wherein the programmable logic device comprises a FPGA.

12. The transceiver of claim 1, wherein the programmable logic device comprises a CPLD or an EPLD.

13. A transceiver, comprising:

an optical interface for detachably coupling to an optical transmission device;

an optical-electrical conversion unit coupled to the optical interface;

a configurable processor communicatively coupled to the optical-electrical conversion unit, wherein the configurable processor is configured to perform packet filtering, packet slicing, time stamping, packet analysis, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof; and

an electrical interface communicatively coupled to the configurable processor, wherein the electrical interface is configured for detachably coupling to an electrical transmission device.

14. The transceiver of claim 13, further comprising:

a diagnostic unit configured to detect a predetermined condition; and

a port coupled to the diagnostic unit for reporting a detection of the predetermined condition.

15. The transceiver of claim 13, further comprising a first end and a second end, wherein the optical interface and the electrical interface are located at the first end, and the configurable processor is located at the second end.

16. The transceiver of claim 13, wherein the configurable processor comprises a clock recovery unit configured to determine time data for time stamping packets received at the transceiver.

17. The transceiver of claim 13, wherein the configurable processor comprises a memory for storing information associated with a processing of packets received at the transceiver.

18. The transceiver of claim 13, further comprising a local clock unit for providing a reference clock signal.

19. The transceiver of claim 13, further comprising a power management unit coupled to the configurable processor, wherein the power management is configured to deactivate the transceiver in response to a detected condition.

20. The transceiver of claim 13, further comprising a configuration port for configuring the configurable processor.

21. The transceiver of claim 13, further comprising an input coupled to the configurable processor for receiving a clock signal from an external clock.

22. The transceiver of claim 13, wherein the configurable processor comprises a FPGA.

23. The transceiver of claim 13, wherein the configurable processor comprises a programmable logic device.

24. A network switch apparatus, comprising:

a network switch housing;

a first network port;

a second network port;

a first instrument port configured to communicate with a monitoring tool; and

a circuit inside the network switch housing, wherein the circuit is configured to receive packets from the first network port, and pass at least some of the packets from the first network port to the first instrument port;

wherein the circuit includes a transceiver located in the network switch housing, and wherein the transceiver includes a configurable processor, and is configured to be detachably coupled to a remaining part of the circuit.

25. The network switch apparatus of claim 24, wherein the configurable processor is configured to perform packet filtering, packet slicing, time stamping, packet analysis, port labeling, packet masking, packet modification, packet stripping, packet de-duplication, or a combination thereof

26. The network switch apparatus of claim 24, wherein the transceiver further includes:

a diagnostic unit configured to detect a predetermined condition; and

a port coupled to the diagnostic unit for reporting a detection of the predetermined condition.

27. The network switch apparatus of claim 24, wherein the transceiver further includes a first end, a second end opposite from the first end, an optical interface, and an electrical interface, wherein the optical interface and the electrical interface are located at the first end, and the configurable processor is located at the second end.

28. The network switch apparatus of claim 24, wherein the configurable processor comprises a clock recovery unit configured to determine time data for time stamping packets received at the transceiver.

29. The network switch apparatus of claim 24, wherein the configurable processor comprises a memory for storing information associated with a processing of packets received at the transceiver.

30. The network switch apparatus of claim 24, wherein the transceiver further includes a local clock unit for providing a reference clock signal.

31. The network switch apparatus of claim 24, wherein the transceiver further includes a power management unit coupled to the configurable processor, wherein the power management is configured to deactivate the transceiver in response to a detected condition.

32. The network switch apparatus of claim 24, wherein the transceiver further includes a configuration port for configuring the configurable processor.

33. The network switch apparatus of claim 24, wherein the transceiver further includes an input coupled to the configurable processor for receiving a clock signal from an external clock.

34. The network switch apparatus of claim 24, wherein the configurable processor comprises a FPGA.

35. The network switch apparatus of claim 24, wherein the configurable processor comprises a programmable logic device.

36. The network switch apparatus of claim 24, wherein the circuit is configured to perform packet transmission in accordance with a predetermined packet movement configuration.

37. The network switch apparatus of claim 36, wherein the packet movement configuration comprises a one-to-one, one-to-many, many-to-one, or a many-to-many configuration.