METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

• US 20130078770A1
• Filed: 09/28/2012
• Published: 03/28/2013
• Est. Priority Date: 09/28/2011
• Status: Active Grant

• Current Assignee: Nitto Denko Corporation
• Original Assignee: Nitto Denko Corporation
• Inventors: Oda, Takashi, Morita, Kosuke, Toyoda, Eiji
• Granted Patent: US 8,580,619 B2
• Time in Patent Office: Days
• US Class Current: 438/127
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68336 involving stretching of the auxiliary support post dicing
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.

Claims

1. A method for producing a semiconductor device including a semiconductor chip, comprising:

preparing a semiconductor chip having a first main surface on which an electroconductive member is formed;

preparing a supporting structure in which over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order;

arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of each of the semiconductor chips that is opposite to the first main surface thereof;

laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and

curing the radiation curable pressure-sensitive adhesive layer by irradiating from a support side to peel the radiation curable pressure-sensitive adhesive layer and the first thermosetting resin layer from each other.

2. The method for producing a semiconductor device according to claim 1, wherein the first thermosetting resin layer has a lowest melt viscosity of 5×

10² Pa·

s or more and 1×

10⁴ Pa·

s or less at a temperature of 50 to 200°

C.

3. The method for producing a semiconductor device according to claim 1, wherein the second thermosetting resin layer is a sheet-like thermosetting resin layer.

4. The method for producing a semiconductor device according to claim 3, wherein the second thermosetting resin layer comprises an epoxy resin, a phenolic resin, a filler, and an elastomer.

5. The method for producing a semiconductor device according to claim 1, further comprising exposing the electroconductive members outward from a surface of the second thermosetting resin layer after the laminating of the second thermosetting resin layer and before the peeling of the radiation curable pressure-sensitive adhesive layer.

6. The method for producing a semiconductor device according to claim 1, further comprising, after the peeling of the radiation curable pressure-sensitive adhesive layer, exposing the electroconductive members outward from the surface of the second thermosetting resin layer.

7. The method for producing a semiconductor device according to claim 5, further comprising forming a rewire connected to the exposed electroconductive members on the second thermosetting resin layer.

8. The method for producing a semiconductor device according to claim 6, further comprising forming a rewire connected to the exposed electroconductive members on the second thermosetting resin layer.