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SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE

  • US 20130080495A1
  • Filed: 11/19/2012
  • Published: 03/28/2013
  • Est. Priority Date: 09/15/2006
  • Status: Active Grant
First Claim
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1. A processor for use in a software based phase locked loop (PLL), comprising:

  • a first adder/subtractor operative to receive input data;

    a shifter operative to shift the output of said first adder/subtractor by a predetermined amount;

    a second adder/subtractor operative to receive the output of said shifter;

    a latch operative to store the output of said second adder/subtractor;

    a plurality of data paths connecting said first adder/subtractor, said shifter, said second adder/subtractor and said latch, said plurality of data paths configurable in accordance with one or more control signals; and

    wherein said processor having an instruction set for controlling said first adder/subtractor, said shifter, said second adder/subtractor, said latch and said plurality of data paths.

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