SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

• US 20130080718A1
• Filed: 08/31/2012
• Published: 03/28/2013
• Est. Priority Date: 09/28/2011
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: HUH, Hwang
• Application Number:
  US13/602,088
• Publication Number:
  US 20130080718A1
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix

Abstract

A semiconductor memory device includes a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line, a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of the memory cells coupled to even word lines, and a second erase verify operation of the memory cells coupled to odd word lines, and an operation circuit, performing the erase operation of the memory cells, applying a first voltage to the odd and even word lines to form a channel in the vertical semiconductor layer between the odd and even word lines when the first and second erase verify operations are performed, respectively.

Claims

1. A semiconductor memory device, comprising:

a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line;

a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of even memory cells coupled to even word lines among the word lines and a second erase verify operation of odd memory cells coupled to odd word lines; and

an operation circuit, controlled by the control circuit, performing the erase operation of the memory cells, applying a first voltage to the odd word lines to form channels in the odd memory cells and channels in the vertical semiconductor layer between the odd word lines and the even word lines when the first erase verify operation is performed, and applying the first voltage to the even word lines to form channels in the even memory cells and channels in the vertical semiconductor layer between the even word lines and the odd word lines when the second erase verify operation is performed.

2. The semiconductor memory device of claim 1, wherein the vertical semiconductor layer vertically extends between the bit line and the source line.

3. The semiconductor memory device of claim 1, wherein the memory string includes a first vertical semiconductor layer vertically extending between the bit line and a pipe channel layer provided on the semiconductor substrate and a second vertical semiconductor layer vertically extending between the pipe channel layer and the source line.

4. The semiconductor memory device of claim 1, wherein the operation circuit is configured to apply a ground voltage to the source line, precharge the bit line, and apply the first voltage to the odd word lines during the first erase verify operation and the second erase verify operation.

5. The semiconductor memory device of claim 1, wherein the operation circuit is configured to apply a second voltage to the even word lines when applying the first voltage to the odd word lines during the first erase verify operation.

6. The semiconductor memory device of claim 1, wherein the operation circuit is configured to apply a second voltage to the even word lines after applying the first voltage to the odd word lines during the first erase verify operation.

7. The semiconductor memory device of claim 1, wherein the operation circuit is configured to apply a second voltage to the odd word lines when applying the first voltage to the even word lines during the second erase verify operation.

8. The semiconductor memory device of claim 1, wherein the operation circuit is configured to apply a second voltage to the odd word lines after applying the first voltage to the even word lines during the second erase verify operation.

9. The semiconductor memory device of claim 5, wherein the second voltage has a lower voltage level than the first voltage.

17. The semiconductor memory device of claim 6, wherein the second voltage has a lower voltage level than the first voltage.

18. The semiconductor memory device of claim 7, wherein the second voltage has a lower voltage level than the first voltage.

19. The semiconductor memory device of claim 8, wherein the second voltage has a lower voltage level than the first voltage.

10. A method of operating a semiconductor memory device, the method comprising:

performing an erase operation on memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory cells coupled between a bit line and a source line and;

forming a channel in the vertical semiconductor layer between odd word lines among the word lines;

performing a first erase verify operation by applying a second voltage to even word lines among the word lines;

forming a channel in the vertical semiconductor layer between the even word lines; and

performing a second erase verify operation by applying the second voltage to the odd word lines.

11. The method of claim 10, wherein a first voltage is applied to the odd word lines to form the channel in the vertical semiconductor layer between the odd word lines.

12. The method of claim 11, wherein the first voltage and the second voltage are applied at the same time.

13. The method of claim 10, wherein a first voltage is applied to the even word lines to form the channel in the vertical semiconductor layer between the even word lines.

14. The method of claim 13, wherein the first voltage and the second voltage are applied at the same time.

15. The method of claim 11, wherein the second voltage has a lower voltage level than the first voltage.

16. The method of claim 10, wherein the first erase verify operation or the second erase verify operation is performed after a ground voltage is applied to the source line and after the bit line is precharged.

20. The method of claim 13, wherein the second voltage has a lower voltage level than the first voltage.