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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

  • US 20130080718A1
  • Filed: 08/31/2012
  • Published: 03/28/2013
  • Est. Priority Date: 09/28/2011
  • Status: Abandoned Application
First Claim
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1. A semiconductor memory device, comprising:

  • a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line;

    a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of even memory cells coupled to even word lines among the word lines and a second erase verify operation of odd memory cells coupled to odd word lines; and

    an operation circuit, controlled by the control circuit, performing the erase operation of the memory cells, applying a first voltage to the odd word lines to form channels in the odd memory cells and channels in the vertical semiconductor layer between the odd word lines and the even word lines when the first erase verify operation is performed, and applying the first voltage to the even word lines to form channels in the even memory cells and channels in the vertical semiconductor layer between the even word lines and the odd word lines when the second erase verify operation is performed.

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