INTEGRATED CIRCUIT WITH A SELF-PROGRAMMED IDENTIFICATION KEY

• US 20130083586A1
• Filed: 09/07/2012
• Published: 04/04/2013
• Est. Priority Date: 09/29/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Inventors: Petitprez, Emmanuel
• Granted Patent: US 8,848,417 B2
• Time in Patent Office: Days
• US Class Current: 365/102
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.

Claims

1. An integrated circuit structure for storing a native binary code, comprising:

a metallization network including a plurality of metallization portions;

an insulating layer positioned on the metallization network; and

an array of planar MIM capacitors on the insulating layer and directly above the metallization portions, respectively, wherein the metallization portions have dimensions configured to produce breakdown voltages in a first group of the MIM capacitors that are smaller by at least 10% than breakdown voltages in a second group of the MIM capacitors, the first group including from 25 to 75% of the MIM capacitors of the array.

2. The native binary code storage structure of claim 1, wherein said metallization portions correspond to copper lines extending parallel to rows or columns of said array.

3. The native binary code storage structure of claim 2, wherein each MIM capacitor is directly above from two to five of the copper lines.

4. The native binary code storage structure of claim 2, wherein the copper lines have a width greater than 1 μ

m and are separated from each other by an interval smaller than 0.5 μ

m, each of the capacitors having lateral dimensions ranging between 2 and 50 μ

m.

5. The native binary code storage structure of claim 1, wherein at least one subset of the MIM capacitors having respective first electrodes that are interconnected.

6. The native binary code storage structure of claim 5, wherein said subset corresponds to a row or to a column of the array.

7. The native binary code storage structure of claim 5, further comprising:

a plurality of selection transistors; and

a plurality of resistors having substantially the same resistance values, wherein the MIM capacitors have respective second electrodes electrically coupled to the selection transistors, respectively, via the resistors, respectively.

8. A method, comprising:

forming integrated circuit structure for storing a native binary code, the forming including;

forming a copper metallization network including a plurality of metallization portions;

forming an insulating layer positioned on the copper metallization network; and

forming an array of planar MIM capacitors on the insulating layer and directly above the metallization portions, respectively, wherein the metallization portions have dimensions configured to produce breakdown voltages in a first group of the MIM capacitors that are smaller by at least 10% than breakdown voltages in a second group of the MIM capacitors, the first group including from 25 to 75% of the MIM capacitors of the array.

9. The method of claim 8, comprising:

programming the native binary code in the integrated circuit structure, the programming including;

commonly connecting at least one subset of the MIM capacitors of said array, in a circuit configured to cause a breakdown of the MIM capacitors in the first group.

10. The method of claim 8, comprising:

electrically coupling first electrodes of the capacitors to a first terminal of a voltage source through a common resistor;

electrically coupling second electrodes of each of the capacitors to a second terminal of the voltage source, via individual resistors; and

applying between the first and second terminals a voltage ranging between breakdown voltages of the MIM capacitors of the first group and breakdown voltages of said MIM capacitors of the second group.

11. The method of claim 10, wherein the number of MIM capacitors multiplied by a ratio between a value of the common resistor and a value of one of the individual resistors is smaller than 0.1.

12. A secure system comprising:

a structure configured to store a native binary code, the structure including;

a metallization network including a plurality of metallization portions;

an insulating layer positioned on the metallization network; and

an array of planar MIM capacitors on the insulating layer and directly above the metallization portions, respectively, wherein the metallization portions have dimensions configured to produce breakdown voltages in a first group of the MIM capacitors that are smaller by at least 10% than breakdown voltages in a second group of the MIM capacitors, the first group including from 25 to 75% of the MIM capacitors of the array; and

a programming circuit configured to cause the MIM capacitors of the first group to breakdown.

13. The system of claim 12, wherein said metallization portions correspond to copper lines extending parallel to rows or columns of said array.

14. The system of claim 13, wherein each MIM capacitor is directly above from two to five of the copper lines.

15. The system of claim 13, wherein the copper lines have a width greater than 1 μ

m and are separated from each other by an interval smaller than 0.5 μ

m, each of the capacitors having lateral dimensions ranging between 2 and 50 μ

m.

16. The system of claim 12, wherein at least one subset of the MIM capacitors having respective first electrodes that are interconnected.

17. The system of claim 16, wherein said subset corresponds to a row or to a column of the array.

18. The system of claim 16, wherein the programming circuit includes:

a plurality of selection transistors; and

a plurality of resistors having substantially the same resistance values, wherein the MIM capacitors have respective second electrodes electrically coupled to the selection transistors, respectively, via the resistors, respectively.

19. A method, comprising:

identifying a native binary code stored in an integrated circuit structure that includes;

a metallization network including a plurality of metallization portions;

an insulating layer positioned on the metallization network; and

an array of planar MIM capacitors on the insulating layer and directly above the metallization portions, respectively, wherein the metallization portions have dimensions configured to produce breakdown voltages in a first group of the MIM capacitors that are smaller by at least 10% than breakdown voltages in a second group of the MIM capacitors, the first group including from 25 to 75% of the MIM capacitors of the array; and

, wherein the identifying includes;

applying a voltage to the array of planar MIM capacitors;

measuring at least one electrical quantity of the array while the voltage is applied to the array, the at least one electrical quantity reflecting breakdown states of the MIM capacitors of the array.

20. The method of claim 19, comprising:

electrically coupling first electrodes of the capacitors to a first terminal of a voltage source through a common resistor;

electrically coupling second electrodes of each of the capacitors to a second terminal of the voltage source, via individual resistors;

electrically coupling the second electrodes of the capacitors to sense amplifiers, respectively, wherein;

applying the voltage includes applying between the first and second terminals a voltage ranging between a breakdown voltages of the MIM capacitors of the first group and breakdown voltages of said MIM capacitors of the second group; and

the measuring includes measuring the at least one electrical quantity using the sense amplifiers.