METHOD FOR FORMATION OF AN ELECTRICALLY CONDUCTING THROUGH VIA

• US 20130084687A1
• Filed: 09/14/2012
• Published: 04/04/2013
• Est. Priority Date: 09/30/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV)
• Inventors: CHAPELON, Laurent-Luc, CUZZOCREA, Julien
• Granted Patent: US 8,673,740 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16148 : the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.

Claims

1-8. -8. (canceled)

9. A method for making a semiconductor device having an electrically conductive through-via within a first semiconductor support having a front face and comprising a silicon substrate, the method comprising:

forming a first insulating layer on the front face of the first semiconductor support;

forming a handle substrate comprising a porous layer, an intermediate semiconductor layer on the porous layer, and a second insulating layer on the intermediate semiconductor layer;

direct bonding the first insulating layer and the second insulating layer; and

thinning the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face; and

forming the electrically conductive through-via.

10. The method of claim 9 wherein forming the electrically conductive through-via comprises forming the electrically conductive through-via from the back face subsequent to the thinning.

11. The method of claim 9 wherein forming the electrically conductive through-via comprises forming the electrically conductive through-via from the front face prior to the thinning, the electrical link then being exposed, after thinning, on the back face.

12. The method of claim 9 further comprising forming the porous layer by at least:

implanting dopant atoms into the handle substrate so as to form a buried doped region on one side of the intermediate semiconductor layer;

forming at least one cavity passing through the intermediate semiconductor layer and opening into the buried doped region; and

forming of a plurality of pores in the buried doped region by an electrochemical process.

13. The method of claim 9 wherein the electrically conductive through-via is formed prior to the thinning by forming a conducting pillar extending from adjacent the front face of the first semiconductor support into the silicon substrate of the first semiconductor support.

14. The method of claim 9 wherein the back face of the first semiconductor support, from where the electrically conductive through-via comes out, is assembled with a front face of a second semiconductor support, the first semiconductor support and the handle substrate forming a three-dimensional integrated structure.

15. The method of claim 9 further comprising fracturing the porous layer so as to separate, on the one side, a residual semiconductor layer and the second insulating layer bonded to an insulating layer of the first semiconductor support, and on the other side, the rest of the rigid additional support.

16. The method of claim 9 wherein the first semiconductor support comprises an interconnection network adjacent the front face thereof, and a conducting pillar formed from a portion of the interconnection network, the conducting pillar passing through the first insulating layer of the first semiconductor support and the second insulating layer, the conducting pillar also protruding from a free face of the first semiconductor support opposite to the back face of the first semiconductor support.

17. The method of claim 14 wherein the second semiconductor support is in a semiconductor wafer.

18. The method of claim 14 wherein the first semiconductor support is formed prior to the assembly step with the second semiconductor support within a semiconductor wafer, the semiconductor support being diced before the assembly step.

19. A method for making a semiconductor device having an electrically conductive through-via within a first semiconductor support having a front face and comprising a silicon substrate, the method comprising:

forming a first insulating layer on the front face of the first semiconductor support;

forming a handle substrate comprising a porous layer, an intermediate semiconductor layer on the porous layer, and a second insulating layer on the intermediate semiconductor layer, the porous layer formed via an electrochemical process;

direct bonding the first insulating layer and the second insulating layer; and

thinning the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face; and

forming the electrically conductive through-via.

20. The method of claim 19 wherein forming the electrically conductive through-via comprises forming the electrically conductive through-via from the back face subsequent to the thinning.

21. The method of claim 19 wherein forming the electrically conductive through-via comprises forming the electrically conductive through-via from the front face prior to the thinning, the electrical link then being exposed, after thinning, on the back face.

22. The method of claim 19 further comprising forming the porous layer by at least:

implanting dopant atoms into the handle substrate so as to form a buried doped region on one side of the intermediate semiconductor layer; and

forming at least one cavity passing through the intermediate semiconductor layer and opening into the buried doped region.

23. The method of claim 19 wherein the electrically conductive through-via is formed prior to the thinning by forming a conducting pillar extending from adjacent the front face of the first semiconductor support into the silicon substrate of the first semiconductor support.

24. The method of claim 19 wherein the back face of the first semiconductor support, from where the electrically conductive through-via comes out, is assembled with a front face of a second semiconductor support, the first and second semiconductor supports forming a three-dimensional integrated structure.

25. The method of claim 19 further comprising fracturing the porous layer so as to separate, on the one side, a residual semiconductor layer and the second insulating layer bonded to an insulating layer of the first semiconductor support, and on the other side, the rest of the rigid additional support.

26. The method of claim 19 wherein the first semiconductor support comprises an interconnection network adjacent the front face thereof, and a conducting pillar formed from a portion of the interconnection network, the conducting pillar passing through the first insulating layer of the first semiconductor support and the second insulating layer, the conducting pillar also protruding from a free face of the first semiconductor support opposite to the back face of the first semiconductor support.

27. The method of claim 24 wherein the second semiconductor support is in a semiconductor wafer.

28. The method of claim 24 wherein the first semiconductor support is formed prior to the assembly step with the second semiconductor support within a semiconductor wafer, the semiconductor support being diced before the assembly step.