Selective Metal Deposition Over Dielectric Layers

• US 20130084699A1
• Filed: 11/27/2012
• Published: 04/04/2013
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Morgan, Paul A., Sinha, Nishant
• Granted Patent: US 9,269,586 B2
• Time in Patent Office: Days
• US Class Current: 438/678
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288

Abstract

Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer.

Claims

1. A method of performing selective electroless plating comprising:

providing a substrate having a first dielectric layer thereover;

forming a conductive layer directly on at least a portion of the first dielectric layer;

forming a hydrogen rich target layer over the conductive layer;

forming an opening to form a contact on the conductive layer;

performing selective electroless plating of a thin film over the contact.

2. The method of claim 1 wherein the target layer is hydrogen rich dielectric.

3. The method of claim 1 wherein the target layer is chlorine rich dielectric.

4. The method of claim 1 further comprising forming a second dielectric layer over the target layer, wherein the second dielectric layer is oxide based.

5. The method of claim 4 wherein the second dielectric layer is formed at a temperature less than 600°

C.

6. The method of claim 1 wherein the second dielectric layer is hydrogen poor relative to the target layer.

7. The method of claim 1 further comprising performing a preclean prior to performing selective electroless plating.

8. The method of claim 1 wherein the thin film comprises one or more members of the group consisting of nickel, thallium, phosphorous, gold, silver, copper, cobalt, palladium, platinum, boron, rhodium, iron, tungsten, binary alloys of these metals and ternary alloys of these metals.

9. The method of claim 1 wherein the thin film comprises a ternary alloy of nickel, thallium and boron.

10. The method of claim 1 wherein the thin film comprises a ternary ally of nickel, phosphorous and copper.

11. The method of claim 1 wherein the first dielectric layer comprises one or more members of the group consisting of SiO₂, doped SiO₂, phosphosilicate glass, tetraethyl orthosilicate, silicon oxynitride and any non-conductive metal nitride.

12. The method of claim 1, wherein after formation of the first dielectric layer, a trench or via is formed in the first dielectric layer and wherein the conductive layer is formed within the via.

13. The method of claim 1 wherein the hydrogen rich target layer is formed over the conductive layer and over the first dielectric layer.

14. The method of claim 1 further comprising performing an activation pretreatment prior to the electroless plating, the pretreatment utilizing one or more of PdCl₂ and a tin-zinc combination.