METHOD OF DIRECT CONNECTING AHCI OR NVMe BASED SSD SYSTEM TO COMPUTER SYSTEM MEMORY BUS

• US 20130086311A1
• Filed: 09/28/2012
• Published: 04/04/2013
• Est. Priority Date: 12/10/2007
• Status: Abandoned Application

• Current Assignee: Ming Huang, Zhiqing Zhuang
• Original Assignee: Ming Huang, Zhiqing Zhuang
• Inventors: Zhuang, Zhiqing, Huang, Ming
• Application Number:
  US13/629,642
• Publication Number:
  US 20130086311A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A SSD system directly connected to the system memory bus includes at least one system memory bus interface unit, one storage controller with associated data buffer/cache, one data interconnect unit, one nonvolatile memory (NVM) module, and flexible association between storage commands and the NVM module. A logical device interface, the Advanced Host Controller Interface (AHCI) or NVM Express (NVMe), is used for the SSD system programming. The SSD system appears to the computer system physically as a dual-inline-memory module (DIMM) attached to the system memory controller, and logically as an AHCI device or an NVMe device. The SSD system may sit in a DIMM socket and scaling with the number of DIMM sockets available to the SSD applications. The invention moves the SSD system from I/O domain to the system memory domain.

Claims

1. A SSD system directly connected to the system memory bus comprising:

at least one system memory bus interface unit (BIU), one storage controller, one data interconnect unit (DIU), one DRAM module, one nonvolatile memory (NVM) module, and flexible association between AHCI/NVMe commands and the NVM module.

2. The system memory bus interface of claim 1 includes a DDR3/DDR4 memory bus interface.

3. The BIU of claim 1 includes an AHCI controller or an NVMe controller.

4. The storage controller of claim 1 performs a programmable classification on a plurality of AHCI/NVMe command queues, terminates all the AHCI/NVMe commands other than NVM read and write commands, and converts the SSD logical block address (LBA) to physical address (PA) and vise versa.

5. The storage controller of claim 1 manages the functions of wear leveling, bad block table, and garbage collection of the SSD.

6. The storage controller of claim 1 generates ECC parity for the write data, and correct data errors with the parity for the corresponding read data.

7. The storage controller of claim 1 randomizes the write data, and de-randomizes the corresponding read data.

8. The storage controller of claim 1 controls the NVM interface timing, and access command sequences.

9. The DRAM module of claim 1 composes DDR3 DRAM, or DDR4 DRAM.

10. The DRAM module of claim 1 is mapped to the system memory domain, and is accessible by both the system memory controller and the storage controller of claim 1.

11. The DRAM module of claim 1 appears to the system memory controller as an UDIMM with additional latency (AL) of 1 or 2 memory clock cycles.

12. The lower N*4KB address space of the DRAM module of claim 1 appears to the system as a memory mapped IO (MMIO) space. The N is application specific. The rest of DRAM module memory address space appears to the system as cacheable memory space.

13. The DIU of claim 1 works as a switch to transfer data between the NVM module and the DRAM module, and between the DRAM module and the system memory controller.

14. In the DIU of claim 1, data transfer between the NVM module and the DRAM module is a background process, which shall pause when the system memory controller accesses the DRAM module.

15. The NVM of claim 1 is but not limited to NAND flash memory, and phase change memory.

16. The NVM modules and the DRAM modules of claim 1 have proprietary pinouts or any one of the standard JEDEC memory module pinouts to plug into the computer system dual in-line memory module (DIMM) sockets.

17. The SSD system of claim 1 is in a single DIMM socket or in a plurality of DIMM sockets.

18. The computer system programs the SSD system of claim 1 as an AHCI device or an NVMe device.

19. The SSD system of claim 1 has at least one interrupt connection to the system to report events to the system CPU.

20. The method of claim 1 wherein the flexible association between AHCI/NVMe commands and the NVM module is provided via the storage controller using both hardware and firmware.