ELECTRICAL MASK INSPECTION

• US 20130087787A1
• Filed: 11/29/2012
• Published: 04/11/2013
• Est. Priority Date: 09/21/2010
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kumar, Arvind, Chou, Anthony I-Chih, Narasimha, Shreesh
• Application Number:
  US13/688,597
• Publication Number:
  US 20130087787A1
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.

Claims

1. A test circuit comprising:

a first endpoint;

a second endpoint;

a first metal layer, comprising a plurality of segments;

a second metal layer, comprising a plurality of segments;

a via layer, comprising a plurality of vias wherein each via is configured and disposed to connect a segment of the first metal layer to a segment of the second metal layer;

wherein the first metal layer comprises a segment connected to said first endpoint and also comprises a segment connected to said second endpoint; and

wherein one of the layers selected from the group consisting of the first metal layer, the second metal layer, and the via layer is a functional layer, and the remaining layers of said group are test layers.

2. The test circuit of claim 1, wherein the via layer is a functional layer, and the first metal layer and second metal layer are test layers.

3. The test circuit of claim 1, wherein the second metal layer is a functional layer, and the first metal layer and the via layer are test layers.

4. The test circuit of claim 1, wherein the first and second endpoints are each comprised of a metal pad.

5. The test circuit of claim 4, wherein the metal pad is square, and has a width and length ranging from about 60 microns to about 100 microns.

6. The test circuit of claim 3, wherein the segments of the first metal layer are 10 percent to 20 percent wider than the segments of the second metal layer.

7-20. -20. (canceled)