Electrical Connection for Chip Scale Packaging

• US 20130087892A1
• Filed: 10/07/2011
• Published: 04/11/2013
• Est. Priority Date: 10/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yew, Ming-Chih, Lin, Wen-Yi, Li, Fu-Jen, Lin, Po-Yao
• Granted Patent: US 9,548,281 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05012 in top view
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/061 Disposition
• CPC Class Codes: H01L 2224/06137 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/06179 Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/141 Disposition
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip'"'"'s direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials'"'"' coefficient of thermal expansion.

Claims

1. A semiconductor device comprising:

a post-passivation layer over a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch; and

a first opening through the post-passivation layer, the first opening having a first dimension and a second dimension less than the first dimension, wherein the first dimension is aligned perpendicular to the first direction of coefficient of thermal expansion mismatch.

2. The semiconductor device of claim 1, further comprising an undercontact metallization layer extending through the first opening.

3. The semiconductor device of claim 1, further comprising a second opening through the post-passivation layer, the second opening being circular in shape.

4. The semiconductor device of claim 1, wherein the first opening is located along an edge of the substrate.

5. The semiconductor device of claim 4, wherein the first opening is located at a corner region of the substrate and the second opening is located along the edge of the substrate.

6. The semiconductor device of claim 4, wherein the second opening is located within an interior region of the substrate.

7. The semiconductor device of claim 1, further comprising a second opening with a third dimension larger than a fourth dimension, the third dimension is aligned perpendicular to a s second direction of coefficient of thermal expansion mismatch.

8. A semiconductor device comprising:

a dielectric layer over a substrate;

a first opening through the dielectric layer, the first opening having a first dimension larger than a second dimension, the first dimension and second dimension being parallel to a major surface of the substrate, wherein the first dimension is aligned perpendicular to a first line extending between a center of the substrate and a center of the first opening; and

a first undercontact metallization extending into the first opening.

9. The semiconductor device of claim 8, further comprising a second opening through the dielectric layer, the second opening having a circular shape.

10. The semiconductor device of claim 9, wherein the first opening is located along an outer edge of the substrate and the second opening is located within an interior region of the substrate.

11. The semiconductor device of claim 9, wherein the first opening is located along an outer edge of the substrate and the second opening is located along the outer edge of the substrate.

12. The semiconductor device of claim 11, wherein the first opening is located in a corner region of the substrate.

13. The semiconductor device of claim 8, further comprising a second opening through the dielectric layer, the second opening having a third dimension larger than a fourth dimension, the third dimension and fourth dimension being parallel to the major surface of the substrate, wherein the third dimension is aligned perpendicular to a second line extending between the center of the substrate and a center of the second opening.

14. A method of manufacturing a semiconductor device, the method comprising:

forming a passivation layer on a substrate, the substrate having a first direction of coefficient of thermal expansion mismatch;

forming a first opening through the passivation layer, the first opening having a first length greater than a first width, the first length aligned perpendicularly with the first direction of coefficient of thermal expansion mismatch; and

forming an undercontact metallization in the first opening.

15. The method of claim 14, wherein the first direction of coefficient of thermal expansion mismatch is aligned with a line between a center of the first opening and a center of the substrate.

16. The method of claim 14, further comprising forming a second opening through the passivation layer, the second opening having a circular shape.

17. The method of claim 16, wherein the first opening is located along an outer edge of the substrate.

18. The method of claim 16, wherein the first opening is located in a corner region of the substrate.

19. The method of claim 14, further comprising testing to determine the first direction of coefficient of thermal expansion mismatch.

20. The method of claim 14, further comprising forming a second opening through the passivation layer, the second opening having a second length greater than a second width, the second length aligned with a second direction of coefficient of thermal expansion mismatch different from the first direction of coefficient of thermal expansion mismatch.