Measuring Capacitance of a Capacitive Sensor with a Microcontroller Having Digital Outputs for Driving a Guard Ring

• US 20130088372A1
• Filed: 10/02/2012
• Published: 04/11/2013
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Lundstrum, Zeke, Curtis, Keith, Davison, Burke, Steedman, Sean, LeFaou, Yann
• Granted Patent: US 9,257,980 B2
• Time in Patent Office: Days
• US Class Current: 341/33
• CPC Class Codes: H03K 17/9622 using a plurality of detectors, e.g. keyboard
• CPC Class Codes: H03K 2217/960725 Charge-transfer
• CPC Class Codes: H03K 2217/960765 Details of shielding arrangements
• CPC Class Codes: H03K 2217/96077 comprising an electrode which is floating

Abstract

A guard ring is provided around each capacitive sensor plate and charged to substantially the same voltage as a voltage on the capacitive sensor plate. The guard ring reduces parasitic capacitances of the capacitive sensor plate caused by differences in voltage potentials between the capacitive sensor plate, and adjacent circuit conductors, ground planes and power planes. Two digital outputs and associated voltage divider resistors are used to drive the guard ring voltage to substantially the same voltage as the voltage on the capacitive sensor plate.

Claims

1. A microcontroller comprising:

a digital processor with memory;

a plurality of external input/output nodes that can be programmed to function as analog nodes,

a multiplexer controlled by the digital processor for selecting one of said analog nodes and coupling the analog node to an analog bus;

an analog-to-digital converter (ADC) coupled with the analog bus for converting an analog voltage on the analog bus to a digital representation thereof and having a digital output coupled to the digital processor for conveying the digital representation; and

an external node coupled to the analog bus.

2. The microcontroller according to claim 1, further comprising a switch between the external node and the analog bus, wherein the switch is programmably controlled by the digital processor.

3. The microcontroller according to claim 1, further comprising at least two digital output nodes of the microcontroller coupled to respective ones of a plurality of digital output drivers.

4. A microcontroller comprising:

a digital processor with memory;

a plurality of digital output drivers controlled by the digital processor;

a sample and hold capacitor;

an analog-to-digital converter (ADC) having a digital output coupled to the digital processor;

at least two digital output nodes of the microcontroller coupled to respective ones of the plurality of digital output drivers;

a first analog node coupled to a first analog bus in the microcontroller;

the first analog bus is switchably coupled to a power supply common, a power supply voltage, the sample and hold capacitor, or a second analog bus;

the second analog bus is switchably coupled to the power supply common, the power supply voltage, the sample and hold capacitor, or the first analog bus; and

the sample and hold capacitor is switchably coupled to either the first analog bus or an input of the ADC.

5. The microcontroller according to claim 4, wherein the first analog node is coupled to the second analog bus and is adapted for coupling to a capacitive sensor.

6. The microcontroller according to claim 4, wherein the at least two digital output nodes are adapted for coupling to a resistor voltage divider network that drives a voltage onto a guard ring associated with the capacitive sensor.

7. The microcontroller according to claim 4, further comprising a second analog node coupled to the second analog bus and adapted for coupling to an external capacitor.

8. The microcontroller according to claim 7, further comprising at least one internal capacitor switchably coupled to the second analog bus.

9. The microcontroller according to claim 4, further comprising a plurality of switches, wherein:

a first one of the plurality of switches couples the first and second analog buses together when closed,

a second one of the plurality of switches couples the first analog bus to a power supply common when closed,

a third one of the plurality of switches couples the second analog bus to a power supply voltage when closed,

a fourth one of the plurality of switches couples the first analog bus to the power supply voltage when closed, and

a fifth one of the plurality of switches couples the second analog bus to the power supply common when closed.

10. The microcontroller according to claim 9, wherein the digital processor controls the plurality of switches.

11. The microcontroller according to claim 9, wherein the plurality of switches are a plurality of field effect transistor (FET) switches.

12. The microcontroller according to claim 4, wherein the plurality of digital output drivers have logic high outputs at substantially the power supply voltage, and logic low outputs at substantially the power supply common.

13. A capacitive sensor system, said system comprising:

a capacitive sensor;

a guard ring associated with the capacitive sensor;

a first resistor coupled to the guard ring;

a second resistor coupled to the guard ring; and

a microcontroller, comprising;

a digital processor with memory;

a plurality of digital output drivers controlled by the digital processor;

a sample and hold capacitor;

an analog-to-digital converter (ADC) having a digital output coupled to the digital processor;

at least two digital output nodes of the microcontroller coupled to respective ones of the plurality of digital output drivers, wherein one of the at least two digital output nodes is coupled to the first resistor and the other one of the at least two digital output nodes is coupled to the second resistor;

a first analog node is coupled to a first analog bus in the microcontroller and the capacitive sensor;

the first analog bus is switchably coupled to a power supply common, a power supply voltage, the sample and hold capacitor, or a second analog bus;

the second analog bus is switchably coupled to the power supply common, the power supply voltage, the sample and hold capacitor, or the first analog bus; and

the sample and hold capacitor is switchably coupled to either the first analog bus or an input of the ADC.

14. The microcontroller according to claim 13, further comprising a second analog node coupled to the second analog bus and adapted for coupling to an external capacitor.

15. The microcontroller according to claim 13, further comprising at least one internal capacitor switchably coupled to the second analog bus.

16. The capacitive sensor system according to claim 13, further comprising a plurality of switches, wherein:

a first one of the plurality of switches couples the first and second analog buses together when closed,

a second one of the plurality of switches couples the first analog bus to a power supply common when closed,

a third one of the plurality of switches couples the second analog bus to a power supply voltage when closed,

a fourth one of the plurality of switches couples the first analog bus to the power supply voltage when closed, and

a fifth one of the plurality of switches couples the second analog bus to the power supply common when closed.

17. The capacitive sensor system according to claim 14, wherein the first resistor is twice the resistance of the second resistor.

18. The capacitive sensor system according to claim 17, wherein a combined capacitive value of the external capacitor and the sample and hold capacitor are approximately one-half the capacitive value of the capacitive sensor.

19. The capacitive sensor system according to claim 13, wherein a voltage on the guard ring is substantially the same as a voltage on the capacitive sensor.

20. The capacitive sensor system according to claim 13, wherein the digital processor controls the plurality of switches.

21. A method for measuring capacitance of a capacitive sensor and controlling a voltage on a guard ring associated with the capacitive sensor, said method comprising the steps of:

providing a capacitive sensor;

providing a guard ring associated with the capacitive sensor;

providing a first resistor coupled to the guard ring;

providing a second resistor coupled to the guard ring; and

providing a microcontroller, comprising;

a digital processor with memory;

a plurality of digital output drivers controlled by the digital processor;

a sample and hold capacitor;

an analog-to-digital converter (ADC) having a digital output coupled to the digital processor;

at least two digital output nodes of the microcontroller coupled to respective ones of the plurality of digital output drivers, wherein one of the at least two digital output nodes is coupled to the first resistor and the other one of the at least two digital output nodes is coupled to the second resistor;

a first analog node is coupled to a first analog bus in the microcontroller and the capacitive sensor;

the first analog bus is switchably coupled to a power supply common, a power supply voltage, the sample and hold capacitor, or a second analog bus;

the second analog bus is switchably coupled to the power supply common, the power supply voltage, the sample and hold capacitor, or the first analog bus; and

the sample and hold capacitor is switchably coupled to either the first analog bus or an input of the ADC; and

performing the steps of;

coupling the sample and hold capacitor to the first analog bus;

coupling the first analog bus to a power supply voltage;

coupling the second analog bus to a power supply common;

driving respective ones of the at least two digital output nodes to substantially the power supply common with outputs from the first and second output drivers;

driving a one of the at least two digital output nodes to substantially the power supply voltage;

driving an other one of the at least two digital output nodes to substantially the power supply common;

coupling the first and second analog buses together long enough for a first charge to settle therebetween;

decoupling the sample and hold capacitor from the first analog bus;

coupling the second analog bus to the power supply common;

coupling the second analog bus to the power supply voltage;

driving the third and fourth analog buses to substantially the power supply voltage;

converting the settled first charge on the sample and hold capacitor to a first digital representation thereof with the ADC;

reading the first digital representation from the ADC with the digital processor;

coupling the first analog bus to the power supply common;

driving the one of the at least two digital output nodes to substantially the power supply common;

driving the other one of the at least two digital output nodes to substantially the power supply voltage;

coupling the first and second analog buses together long enough for a second charge to settle therebetween;

decoupling the sample and hold capacitor from the first analog bus;

coupling the second analog bus to the power supply voltage;

coupling the second analog bus to the power supply common;

driving the third and fourth analog buses to substantially the power supply common;

converting the settled second charge on the sample and hold capacitor to a second digital representation thereof with the ADC; and

reading the second digital representation from the ADC with the digital processor.

22. The method according to claim 21, further comprising the step of processing the first and the second digital representations with the digital processor to substantially reduce common mode noise.

23. The method according to claim 21, further comprising the steps of:

storing the first and the second digital representations in a memory associated with the digital processor;

comparing the stored first and second digital representations with subsequent first and second digital representations, wherein

if the stored first and second digital representations are substantially the same as the subsequent first and second digital representations then the capacitive sensor is not actuated, and

if the stored first and second digital representations are not substantially the same as the subsequent first and second digital representations then the capacitive sensor is actuated.

24. A method for measuring capacitance of a capacitive sensor and controlling a voltage on a guard ring associated with the capacitive sensor, said method comprising the steps of:

a) charging a sample and hold capacitor to a first voltage;

b) charging a capacitive sensor to a second voltage;

c) charging a guard ring associated with the capacitive sensor to the second voltage;

d) charging the guard ring to a third voltage;

e) coupling together the sample and hold capacitor and the capacitive sensor long enough for a first charge to settle therebetween;

f) decoupling the sample and hold capacitor from the capacitive sensor;

g) converting the settled first charge on the sample and hold capacitor to a first digital representation thereof with an analog-to-digital converter (ADC);

h) charging the capacitive sensor to the second voltage;

i) charging the capacitive sensor to the first voltage;

j) charging the guard ring to the first voltage;

k) reading the first digital representation of the first charge from the ADC with a digital processor;

l) charging the guard ring to a fourth voltage;

m) coupling together the sample and hold capacitor and the capacitive sensor long enough for a second charge to settle therebetween;

n) decoupling the sample and hold capacitor from the capacitive sensor;

o) converting the settled second charge on the sample and hold capacitor to a second digital representation thereof with the analog-to-digital converter (ADC);

p) charging the capacitive sensor to the first voltage;

q) charging the capacitive sensor to the second voltage;

r) charging the guard ring to the second voltage;

s) reading the second digital representation of the second charge from the ADC with the digital processor; and

t) returning to step d).

25. The method according to claim 24, wherein the first voltage is approximately a power supply voltage and the second voltage is approximately a power supply common.

26. The method according to claim 24, wherein the first voltage is approximately a power supply common and the second voltage is approximately a power supply voltage.

27. The method according to claim 24, wherein a voltage on the guard ring is substantially the same as a voltage on the capacitive sensor.