DISTURB VERIFY FOR PROGRAMMING MEMORY CELLS

• US 20130088916A1
• Filed: 10/06/2011
• Published: 04/11/2013
• Est. Priority Date: 10/06/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira, Sarpatwari, Karthik
• Granted Patent: US 8,638,607 B2
• Time in Patent Office: Days
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation. Other apparatuses and methods are also disclosed.

Claims

1. A method for programming memory cells, comprising:

applying a number of programming pulses to a first memory cell;

performing a disturb verify operation on a second memory cell adjacent to the first memory cell; and

inhibiting the first memory cell from programming in response to the second memory cell failing the disturb verify operation.

2. The method of claim 1, wherein the method includes enabling programming of the first memory cell in response to the second memory cell passing the disturb verify operation.

3. The method of claim 1, wherein performing the disturb verify operation on a second memory cell adjacent to the first memory cell comprises performing the disturb verify operation on the second memory cell if the second memory cell is in a lowermost data state of a number of data states and a target data state of the first memory cell is an uppermost data state of the number of data states.

4. The method of claim 3, wherein applying a number of programming pulses to a first memory cell comprises applying the number of programming pulses to the first memory cell and a third memory cell adjacent to the second memory cell, and performing a disturb verify operation on a second memory cell adjacent to the first memory cell comprises performing the disturb verify operation on the second memory cell if the second memory cell is in an erased state and a target data state of the first memory cell and the third memory cell is an uppermost data state of a number of data states.

5. The method of claim 1, wherein performing a disturb verify operation includes determining whether a threshold voltage of the second memory cell exceeds a particular threshold corresponding to a target data state of the second memory cell.

6. A method for programming memory cells, comprising:

applying a number of programming pulses to a first memory cell;

determining whether a threshold voltage of a second memory cell adjacent to the first memory cell exceeds a disturb threshold; and

inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold.

7. The method of claim 6, wherein the method includes determining whether a threshold voltage of the first memory cell exceeds a critical threshold level, and wherein inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold comprises inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold and the threshold voltage of the first memory cell exceeding the critical threshold level.

8. The method of claim 6, wherein the method includes determining whether the number of programming pulses exceeds a threshold number of programming pulses, and wherein inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold comprises inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold and the number of programming pulses exceeding the threshold number of programming pulses.

9. The method of claim 6, wherein the method includes determining whether a number of sacrificed memory cells in a page of memory cells exceeds a threshold number of sacrificed memory cells, and wherein inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold comprises inhibiting further programming of the first memory cell in response to the threshold voltage of the second memory cell exceeding the disturb threshold and the number of sacrificed memory cells not exceeding the threshold number of sacrificed memory cells, wherein the page of memory cells includes the first memory cell.

10. The method of claim 6, wherein applying a number of programming pulses to a first memory cell comprises applying the number of programming pulses to the first memory cell and a third memory cell adjacent to the second memory cell, and wherein determining whether a threshold voltage of a second memory cell adjacent to the first memory cell exceeds a disturb threshold comprises determining whether the threshold voltage of the second memory cell adjacent to the first memory cell exceeds the disturb threshold if the second memory cell is in a lowermost data state of a number of data states and if the first memory cell and the third memory cell have a target data state that is an uppermost data state of the number of data states.

11. A method for programming memory cells, comprising:

applying a number of programming pulses to a first memory cell and a third memory cell that are adjacent to a second memory cell;

performing a disturb verify operation on the second memory cell;

inhibiting at least one of the first and the third memory cells from further programming in response to the second memory cell failing the disturb verify operation.

12. The method of claim 11, wherein the method includes selectively disabling the disturb verify operation.

13. The method of claim 11, wherein the method includes applying an additional programming pulse to the first and the third memory cells after performing the disturb verify operation.

14. The method of claim 11, wherein inhibiting at least one of the first and the third memory cells from further programming comprises inhibiting both of the first and the third memory cells from further programming.

15. The method of claim 11, wherein inhibiting at least one of the first and the third memory cells from further programming comprises inhibiting only one of the first and the third memory cells from further programming.

16. A method for programming memory cells, comprising:

determining whether a threshold voltage of a first memory cell coupled to an access line exceeds a disturb threshold; and

applying a program inhibit signal to a data line to program inhibit a second memory cell in response to the threshold voltage of the first memory cell exceeding the disturb threshold, wherein the second memory cell is coupled to the access line and is adjacent to the first memory cell.

17. The method of claim 16, wherein applying a program inhibit signal to a data line to program inhibit a second memory cell in response to the threshold voltage of the first memory cell exceeding the disturb threshold comprises applying the program inhibit signal to the data line if the first memory cell is in a lowermost data state of a number of data states.

18. The method of claim 17, wherein the method further includes applying the program inhibit signal to another data line to program inhibit a third memory cell in response to the threshold voltage of the first memory cell exceeding the disturb threshold, wherein the third memory cell is adjacent to the first memory cell and coupled to the access line.

19. The method of claim 16, wherein the method includes determining whether the threshold voltage of the first memory cell exceeds the disturb threshold in response to determining that a threshold voltage of the second memory cell does not exceed a program verify threshold corresponding to a target data state of the second memory cell.

20. The method of claim 16, wherein the first memory cell is part of a first page of memory cells and the second memory cell is part of a second page of memory cells, wherein the first page and the second page are different pages.

21. The method of claim 16, wherein the method includes determining whether the threshold voltage of the first memory cell exceeds the disturb threshold in response to a number of programming pulses applied to the second memory cell exceeding a threshold number of programming pulses.

22. The method of claim 16, wherein the method includes counting a number of memory cells in a page that includes the second memory cell that fail a disturb verify operation.

23. The method of claim 22, wherein applying a program inhibit signal to a data line to program inhibit a second memory cell in response to the threshold voltage of the first memory cell exceeding the disturb threshold comprises applying the program inhibit signal only if the number of memory cells does not exceed a threshold number of memory cells.

24. The method of claim 22, wherein the method includes skipping a subsequent disturb verify operation in response to the number of memory cells that fail the disturb verify operation exceeding a fail threshold.

25. An apparatus, comprising:

an array of memory cells; and

control circuitry coupled to the array, wherein the control circuitry is configured to;

apply a number of programming pulses to a first memory cell of the array;

perform a disturb verify operation on a second memory cell of the array, wherein the second memory cell is adjacent to the first memory cell; and

enable further programming of the first memory cell in response to the second memory cell passing the disturb verify operation.

26. The apparatus of claim 25, wherein the control circuitry is configured to inhibit the first memory cell from further programming in response to the second memory cell failing the disturb verify operation.

27. The apparatus of claim 26, wherein the control circuitry is further configured to determine a number of sacrificed memory cells in a page of the array including the first memory cell and wherein the control circuitry being configured to inhibit the first memory cell from further programming comprises the control circuitry being configured to inhibit the first memory cell from further programming in response to the second memory cell passing the disturb verify operation and the number of sacrificed memory cells not exceeding a threshold number of sacrificed memory cells.

28. The apparatus of claim 25, wherein the control circuitry being configured to perform a disturb verify operation on a second memory cell comprises the control circuitry being configured to perform the disturb verify operation on the second memory cell only if the second memory cell is in a lowermost data state of a number of data states.

29. The apparatus of claim 25, wherein the control circuitry being configured to perform a disturb verify operation on a second memory cell comprises the control circuitry being configured perform the disturb verify operation on the second memory cell only if the second memory cell is in a data state below a threshold data state.

30. The apparatus of claim 25, wherein the control circuitry is further configured to determine the number of programming pulses applied to the first memory cell during a programming operation, and is further configured to perform the disturb verify operation in response to the number of programming pulses exceeding a threshold number of programming pulses.

31. An apparatus, comprising:

an array of memory cells; and

control circuitry coupled to the array, wherein the control circuitry is configured to;

apply a number of programming pulses to a first memory cell of the array and a third memory cell of the array, wherein the first and the second memory cells are adjacent to a second memory cell of the array;

perform a disturb verify operation on the second memory cell;

inhibit at least one of the first and the third memory cells from further programming in response to the second memory cell failing the disturb verify operation.

32. The apparatus of claim 31, wherein the control circuitry being configured to perform a disturb verify operation on the second memory cell comprises the control circuitry being configured to perform the disturb verify operation on the second memory cell if the first and the third memory cells have a target data state of an uppermost data state of a number of data states.

33. The apparatus of claim 31, wherein the control circuitry is configured to perform the disturb verify operation by applying a sensing voltage to the second memory cell, wherein the sensing voltage is greater than an uppermost voltage associated with an erased state.

34. The apparatus of claim 33, wherein the sensing voltage is negative.

35. The apparatus of claim 31, further including a host coupled to the control circuitry.